公开(公告)号：US6130132A

公开(公告)日：2000-10-10

申请号：US55439

申请日：1998-04-06

申请人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L27/11521 ,  H01L21/28273

摘要： The following steps are used to form a split gate electrode MOS FET device. Form a tunnel oxide layer over a semiconductor substrate. Over the tunnel oxide layer, form a doped first polysilicon layer with a top surface upon which a native oxide forms. Then as an option, remove the native oxide layer. On the top surface of the first polysilicon layer, form a silicon nitride layer and etch the silicon nitride layer to form it into a cell-defining layer. Form a polysilicon oxide dielectric cap over the top surface of the first polysilicon layer. Aside from the polysilicon oxide cap, etch the first polysilicon layer and the tunnel oxide layer to form a floating gate electrode stack in the pattern of the masking cap forming a sharp peak on the periphery of the floating gate electrode. Form spacers on the sidewalls of the gate electrode stack. Then form blanket inter-polysilicon dielectric and blanket control gate layers covering exposed portions of the substrate and covering the stack. Pattern the inter-polysilicon dielectric and control gate layers into a split gate electrode pair. Form a source region self-aligned with the floating gate electrode stack; perform a tungsten silicide anneal; and form a drain region self-aligned with the control gate electrodes.

摘要翻译： 以下步骤用于形成分离栅电极MOS FET器件。 在半导体衬底上形成隧道氧化层。 在隧道氧化物层上形成掺杂的第一多晶硅层，其上形成有天然氧化物的顶表面。 然后作为选项，删除自然氧化物层。 在第一多晶硅层的顶表面上，形成氮化硅层并蚀刻氮化硅层以形成单元限定层。 在第一多晶硅层的顶表面上形成多晶硅氧化物电介质盖。 除了多晶硅氧化物盖之外，蚀刻第一多晶硅层和隧道氧化物层以形成掩模帽图案中的浮栅电极堆叠，在浮栅电极的外围形成尖锐的峰。 在栅极电极堆叠的侧壁上形成间隔物。 然后形成覆盖基板的暴露部分并覆盖堆叠的覆盖层间多晶硅电介质和覆盖层控制栅极层。 将多晶硅间介质和控制栅极层图案化成分离栅电极对。 形成与浮栅电极堆叠自对准的源区; 进行硅化钨退火; 并形成与控制栅电极自对准的漏区。

公开(公告)号：US6117733A

公开(公告)日：2000-09-12

申请号：US193670

申请日：1998-11-17

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

IPC分类号： H01L21/8247 ,  H01L29/423 ,  H01L21/336 ,  H01L29/72 ,  H01L31/00

CPC分类号： H01L29/42324 ,  H01L27/11519 ,  H01L27/11521

摘要： A novel method of forming a first polysilicon gate tip (poly tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly tip is further enhanced by forming a notch in two different ways in a nitride layer overlying the first polysilicon layer. In one embodiment, the notch is formed after wet oxidizing the sidewalls of the underlying first polysilicon layer, thus at the same time forming a poly tip which is exposed upwardly but covered by polyoxide on the side. In another embodiment, the notch is formed prior to the oxidation of the exposed regions of the first polysilicon layer, such as the sidewalls, so that during the subsequent oxidation, not only the sidewalls but also the exposed portions of the polysilicon in the notch region are also oxidized. Because the oxidation of the polysilicon advances in a non-uniform manner with very little at the polysilicon/nitride interface and to a larger rate elsewhere, a thin and robust polysilicon tip is formed which is at the same time covered by oval-shaped poly-oxide on all sides. A method of forming a self-aligned source (SAS) line is also disclosed in conjunction with the forming of the polytip. Hence the combination of an enhanced poly tip with a self-aligned source provides a faster split-gate flash memory device.

摘要翻译： 公开了一种用于形成分裂栅闪存单元中用于增强的F-N隧穿的第一多晶硅栅尖（多头）的新方法。 通过在覆盖第一多晶硅层的氮化物层中以两种不同的方式形成凹口来进一步增强多晶硅尖端。 在一个实施例中，凹陷是在湿氧化下面的第一多晶硅层的侧壁之后形成的，因此同时形成向上暴露但被侧面被多氧化物覆盖的多边尖端。 在另一个实施例中，在第一多晶硅层（例如侧壁）的暴露区域的氧化之前形成凹口，使得在随后的氧化期间，不仅侧壁而且在凹口区域中的多晶硅的暴露部分 也被氧化。 由于多晶硅的氧化以非均匀的方式在多晶硅/氮化物界面处以非常小的速度前进，并且在其它地方以更大的速率前进，形成了薄而坚固的多晶硅尖端，同时被椭圆形多晶硅/ 氧化物在所有方面。 结合形成聚丝片也公开了形成自对准源（SAS）线的方法。 因此，增强型多头尖端与自对准源的组合提供了更快的分离栅极闪存器件。

公开(公告)号：US6090668A

公开(公告)日：2000-07-18

申请号：US248725

申请日：1999-02-11

申请人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Jung-Ke Yeh ,  Chang-Song Lin ,  Di-Son Kuo

发明人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Jung-Ke Yeh ,  Chang-Song Lin ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L29/423

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42324

摘要： A method is provided for forming a split-gate flash memory cell having a sharp poly tip which substantially improves the erase speed of the cell. The poly tip is formed without the need for conventional oxidation of the polysilicon floating gate. Instead, the polysilicon layer is etched using a high pressure recipe thereby forming a recess with a sloped profile into the polysilicon layer. The recess is filled with a top-oxide, which in turn serves as a hard mask in etching those portions of the polysilicon year not protected by the top-oxide layer. The edge of the polysilicon layer formed by the sloping walls of the recess forms the sharp poly tip of this invention. The sharp tip does not experience the damage caused by conventional poly oxidation processes and, therefore, provides enhanced erase speed for the split-gate flash memory cell. The invention is also directed to a semiconductor device fabricated by the disclosed method.

摘要翻译： 提供了一种用于形成具有尖锐多边尖端的分裂栅极闪存单元的方法，其基本上改善了单元的擦除速度。 形成多边形，而不需要多晶硅浮动栅极的常规氧化。 相反，使用高压配方蚀刻多晶硅层，从而形成具有倾斜轮廓的凹陷到多晶硅层中。 凹部填充有顶部氧化物，其又用作蚀刻多晶硅年份未被顶部氧化物层保护的那些部分的硬掩模。 由凹陷的倾斜壁形成的多晶硅层的边缘形成本发明的尖锐的多边形尖端。 锋利的尖端不会经历由常规聚氧化过程引起的损坏，因此为分离式闪存单元提供增强的擦除速度。 本发明还涉及通过所公开的方法制造的半导体器件。

公开(公告)号：US06249454B1

公开(公告)日：2001-06-19

申请号：US09396519

申请日：1999-09-15

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

IPC分类号： G11C1604

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L27/115

摘要： In this invention bit lines are ion implanted into a semiconductor substrate in columns beside floating gates of an array of flash memory cells. A control gate overlays each row floating gates and operates as a word lines for the rows of flash memory cells. Each bit line serves a dual purpose of providing a drain for one cell and a source for the adjacent cell. The flash memory cells are programmed, erased and read depending upon the voltages applied to the buried bit lines and the word line structured as a control gate that extends the length of each row. By implanting the bit lines into the semiconductor substrate the flash memory cell can be made smaller improving the density of the flash memory.

公开(公告)号：US06207503B1

公开(公告)日：2001-03-27

申请号：US09133970

申请日：1998-08-14

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern a gate electrode stack formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Form intermetal dielectric and control gate layers over the substrate covering the stack and the source regions and the drain regions. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Pattern a source line slot in the center of the gate electrode stack down to the substrate. Form source regions through the source line slot. Form drain regions self-aligned with the split gate electrodes and the gate electrode stack.

摘要翻译： 形成分离栅电极MOSFET器件的方法包括以下步骤。 在半导体衬底上形成隧道氧化层。 在隧道氧化物层上形成浮栅电极层。 在浮栅电极层上形成掩蔽帽。 以掩模盖的图案形成由隧道氧化物层和浮栅电极层形成的栅电极堆叠。 在覆盖堆叠和源极区域和漏极区域的衬底上方形成金属间电介质和控制栅极层。 将金属间电介质和控制栅极层图案化成相邻的镜像分离栅电极对。 将栅极电极堆叠的中心的源极线槽图案化为衬底。 通过源线槽形成源区。 形成漏极区域与分离栅电极和栅极电极堆叠自对准。

公开(公告)号：US6093608A

公开(公告)日：2000-07-25

申请号：US298142

申请日：1999-04-23

申请人： Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Chia-Ta Hsieh

发明人： Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Chia-Ta Hsieh

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L21/8247

CPC分类号： H01L29/42324 ,  H01L21/28273

摘要： A split gate P-channel flash memory cell and method of forming a split gate P-channel flash memory cell which avoids of high erasing voltage, reverse tunneling during programming, drain disturb and over erase problems, and permits shrinking the cell dimensions. The control gate has a concave top surface which intersects with the sidewalls to form a sharp edge. The cell is programmed by charging the floating gate with electrons by means of hot electron injection from the channel into the floating gate. The cell is erased by discharging the excess electrons from the floating gate into the control gate using Fowler-Nordheim tunneling. The sharp edge at the intersection of the concave top surface and the sidewalls of the floating gate produces a high electric field between the control gate and the floating gate to accomplish the Fowler-Nordheim tunneling with only moderate voltage differences between the floating gate and control gate. The P-channel flash memory cell has a higher impact ionization rage for creating hot electrons so that the distance between the source and drain junctions and the length of the floating gate can be kept small thereby permitting the dimensions of the flash memory cell to be shrunk.

公开(公告)号：US6046086A

公开(公告)日：2000-04-04

申请号：US100691

申请日：1998-06-19

申请人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Di-Son Kuo

发明人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Di-Son Kuo

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521 ,  Y10S438/981

摘要： A method is provided for forming a split-gate flash memory cell having reduced size, increased capacitive coupling and improved data retention capability. A split-gate cell is also provided with appropriate gate oxide thicknesses between the substrate and the floating gate and between the floating gate and the control gate along with an extra thin nitride layer formed judiciously over the primary gate oxide layer in order to overcome the problems of low data retention capacity of the floating gate and the reduced capacitive coupling between the floating gate and the source of prior art.

摘要翻译： 提供了一种用于形成具有减小的尺寸，增加的电容耦合和改进的数据保持能力的分离栅极闪存单元的方法。 分离栅极单元还在衬底和浮置栅极之间以及浮置栅极和控制栅极之间提供适当的栅极氧化物厚度，以及在主栅极氧化物层上明智地形成的额外的薄的氮化物层，以克服问题 的浮动栅极的低数据保持容量和现有技术的浮动栅极和源极之间的减小的电容耦合。

公开(公告)号：US5976927A

公开(公告)日：1999-11-02

申请号：US58120

申请日：1998-04-10

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Hung-cheng Sung

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Hung-cheng Sung

IPC分类号： H01L21/762 ,  H01L21/8242 ,  H01L21/8247 ,  H01L21/76

CPC分类号： H01L27/10844 ,  H01L21/76202 ,  H01L27/11517

摘要： A method for forming a field oxide isolation regions of a memory array is described. The field isolation regions comprise a rectangular array of oxide islands. The oxide islands are formed by a two mask process wherein the first mask is a LOCOS hardmask which defines an array of parallel field oxide stripes. The field oxide stripes are thermally grown by a LOCOS oxidation process. A second mask, which has an array of parallel stripes perpendicular to the field oxide stripes is then patterned over the wafer. The stripes of the second mask expose a plurality of narrow sections of the field oxide stripes which are then etched by a directional plasma etch having a high selectivity of silicon oxide over silicon. The anisotropic etch segments each of the longer oxide stripes into a string of islands space apart by a narrow gap through which a robust common source line passes unencumbered by birdsbeak oxide. The edges of the field oxide at the gap have vertical walls and square corners which afford improved spacing of components in the vicinity of the gap. The method eliminates the need for a mask bias to accommodate corner rounding and birdsbeak oxide encroachment which occurs if the islands are defined by a single mask process.

摘要翻译： 描述了形成存储器阵列的场氧化物隔离区域的方法。 场隔离区域包括氧化物岛的矩形阵列。 氧化物岛通过两个掩模工艺形成，其中第一掩模是定义平行场氧化物条纹阵列的LOCOS硬掩模。 场氧化物条纹通过LOCOS氧化工艺热生长。 然后将具有垂直于场氧化物条纹的平行条纹阵列的第二掩模图案化在晶片上。 第二掩模的条纹暴露出场氧化物条纹的多个窄部分，然后通过硅上的氧化硅选择性高的定向等离子体蚀刻来蚀刻。 各向异性蚀刻将较长的氧化物条中的每一个划分成岛状空间，间隔狭窄的间隙，坚固的公共源极线穿过该间隙不受鸟笼氧化物阻碍。 间隙处的场氧化物的边缘具有垂直壁和方角，其提供间隙附近的部件的间隔改善。 该方法消除了掩模偏压的需要，以适应拐角倒圆和鸟瞰氧化物侵蚀，如果岛由单个掩模过程定义，则会发生。

公开(公告)号：US06674118B2

公开(公告)日：2004-01-06

申请号：US09876596

申请日：2001-06-08

申请人： Chung-Ker Yeh ,  Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

发明人： Chung-Ker Yeh ,  Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

IPC分类号： H01L29788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11531

摘要： A PIP (Poly-Interpoly-Poly) capacitor with high capacitance is provided in a split-gate flash memory cell. A method is also disclosed to form the same PIP capacitor where the bottom and top plates of the capacitor are formed simultaneously with the floating gate and control gate, respectively, of the split-gate flash memory cell. Furthermore, the thin interpoly oxide of the cell, rather than the thick poly-oxide over the floating gate is used as the insulator between the plates of the capacitor. The resulting capacitor yields high storage capacity through high capacitance per unit area.

摘要翻译： 在分闸式闪存单元中提供了具有高电容的PIP（Poly-Poly Poly Poly-Poly）电容器。 还公开了一种形成相同的PIP电容器的方法，其中电容器的底板和顶板分别与分闸器闪存单元的浮置栅极和控制栅极同时形成。 此外，电池的薄的多晶硅氧化物，而不是浮栅上的厚多晶氧化物，被用作电容器板之间的绝缘体。 所产生的电容通过每单位面积的高电容产生高存储容量。

公开(公告)号：US06441429B1

公开(公告)日：2002-08-27

申请号：US09621378

申请日：2000-07-21

申请人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Di-Son Kuo

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L21/28273

摘要： A split gate electrode MOS FET device includes a tunnel oxide layer formed over a semiconductor substrate. Over the tunnel oxide layer, a doped first polysilicon layer is formed with a top surface. A native oxide which forms over the doped first polysilicon layer may have been removed as an option. On the top surface of the first polysilicon layer, a silicon nitride layer was etched to form it into a cell-defining layer. A polysilicon oxide dielectric cap was formed over the top surface of the first polysilicon layer. Aside from the polysilicon oxide cap, the first polysilicon layer and the tunnel oxide layer were formed into a floating gate electrode stack in the pattern of the masking cap forming a sharp peak on the periphery of the floating gate electrode. Spacers are formed on the sidewalls of the gate electrode stack. Blanket inter-polysilicon dielectric and blanket control gate layers cover exposed portions of the substrate and the stack. The inter-polysilicon dielectric and control gate layers are patterned into a split gate electrode pair. A source region is self-aligned with the floating gate electrode stack. A tungsten silicide anneal was performed; and a drain region self-aligned with the control gate electrodes was formed.

摘要翻译： 分离栅电极MOS FET器件包括形成在半导体衬底上的隧道氧化物层。 在隧道氧化物层之上，掺杂的第一多晶硅层形成有顶表面。 在掺杂的第一多晶硅层上形成的自然氧化物可以作为选择被去除。 在第一多晶硅层的顶表面上蚀刻氮化硅层以形成单元限定层。 在第一多晶硅层的顶表面上形成多晶硅氧化物电介质盖。 除了多晶硅氧化物盖之外，第一多晶硅层和隧道氧化物层以掩模盖的图案形成浮栅电极堆叠，在浮栅电极的周围形成尖锐的峰。 隔板形成在栅电极堆叠的侧壁上。 毯状多晶硅间介质和覆盖层控制栅极层覆盖基板和堆叠的暴露部分。 多晶硅间介质层和控制栅极层被图案化成分裂栅电极对。 源区域与浮栅电极堆叠自对准。 进行硅化钨退火; 并且形成与控制栅极电极自对准的漏极区域。