公开(公告)号：US06787416B2

公开(公告)日：2004-09-07

申请号：US10253039

申请日：2002-09-24

申请人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Hung

发明人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Hung

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： The present invention includes devices and methods to form non-volatile memory cells and peripheral devices, with reduced damage to the electron trapping layer and, optionally, reduced thermal exposure during CMOS processing. Particular aspects of the present invention are described in the claims, specification and drawings.

摘要翻译： 本发明包括用于形成非易失性存储器单元和外围设备的装置和方法，对电子俘获层的损害降低，并且可选地在CMOS处理期间减少热暴露。 在权利要求书，说明书和附图中描述了本发明的特定方面。

公开(公告)号：US06559010B1

公开(公告)日：2003-05-06

申请号：US10003320

申请日：2001-12-06

申请人： Tung-Cheng Kuo ,  Shou-Wei Hwang ,  Chien-Hung Liu ,  Shyi-Shuh Pan

发明人： Tung-Cheng Kuo ,  Shou-Wei Hwang ,  Chien-Hung Liu ,  Shyi-Shuh Pan

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： A method is described for forming a non-volatile memory comprising dividing a substrate into at least a memory array area and a logic device area. An oxide/nitride/oxide (ONO) layer is firstly formed on the substrate, and a photoresist layer is formed on the ONO layer by bit line photo process, and a bit line ion implantation process is performed on the substrate to form the plurality of bit lines structure. Then, a first polysilicon layer is deposited to form a plurality of word lines by word line photo condition. The complementary metal-oxide-semiconductor (CMOS) ONO layer is used to store the charge and the ONO layer is only touched by the photoresist layer once. Furthermore, the separated adjust photo condition of the memory array area and the logic device area can create a safe oxide thickness to solve the problem of leakage path between bit lines to bit lines by using a self-aligned silicide process.

摘要翻译： 描述了一种用于形成非易失性存储器的方法，包括将衬底划分成至少存储器阵列区域和逻辑器件区域。 首先在衬底上形成氧化物/氮化物/氧化物（ONO）层，并且通过位线光刻工艺在ONO层上形成光致抗蚀剂层，并在衬底上进行位线离子注入工艺以形成多个 位线结构。 然后，通过字线照片条件沉积第一多晶硅层以形成多个字线。 互补金属氧化物半导体（CMOS）ONO层用于存储电荷，并且ONO层仅被光致抗蚀剂层触及一次。 此外，存储器阵列区域和逻辑器件区域的分离的调整照相条件可以产生安全的氧化物厚度，以通过使用自对准硅化物处理来解决位线到位线之间的泄漏路径的问题。

公开(公告)号：US06436800B1

公开(公告)日：2002-08-20

申请号：US09990393

申请日：2001-11-20

申请人： Tung-Cheng Kuo ,  Shou-Wei Hung ,  Chien-Hung Liu ,  Shyi-Shuh Pan

发明人： Tung-Cheng Kuo ,  Shou-Wei Hung ,  Chien-Hung Liu ,  Shyi-Shuh Pan

IPC分类号： H01L2138

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： A fabrication method for a nonvolatile memory with a shallow junction is described. A gate structure, comprising an electron-trapping layer and a conductive layer, is formed on a substrate. A doped spacer is formed on the sidewall of the gate structure. Buried bit lines are further formed in the substrate beside the gate structure. Thereafter, thermal process is conducted to diffuse the dopants from the doped spacer into the substrate adjacent to the buried bit lines.

摘要翻译： 描述了一种具有浅结的非易失性存储器的制造方法。 在基板上形成包括电子捕获层和导电层的栅极结构。 掺杂间隔物形成在栅极结构的侧壁上。 在栅极结构旁边的衬底中进一步形成掩埋位线。 此后，进行热处理以将掺杂的掺杂剂从埋入的位线扩散到衬底中。

公开(公告)号：US06511882B1

公开(公告)日：2003-01-28

申请号：US09990287

申请日：2001-11-23

申请人： Tung-Cheng Kuo ,  Shou-Wei Hwang ,  Chien-Hung Liu ,  Shyi-Shuh Pan

发明人： Tung-Cheng Kuo ,  Shou-Wei Hwang ,  Chien-Hung Liu ,  Shyi-Shuh Pan

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： A method for forming an embedded non-volatile memory is disclosed. The embedded non-volatile memory, comprises memory array and logic device area, is formed on a substrate where an oxide/nitride/oxide (ONO) layer on a memory array, a gate oxide layer on a logic device area. The method is that transistors of memory array and transistors of logic device area are formed by two separately photolithography processes. In memory array, the pitch between the poly gate electrodes is equivalent and has wider spacer width. In logic device area, the pitch between the poly gate electrodes is different and has suitable spacer width. According to above-mentioned, by using separated spacer width in memory array and logic device area can avoid the leakage path between bit line to bit line in subsequently self-aligned salicide process.

摘要翻译： 公开了一种用于形成嵌入式非易失性存储器的方法。 在存储器阵列上的氧化物/氮化物/氧化物（ONO）层，逻辑器件区域上的栅极氧化物层的衬底上形成包括存储器阵列和逻辑器件区域的嵌入式非易失性存储器。 该方法是存储器阵列的晶体管和逻辑器件区域的晶体管由两个分开的光刻工艺形成。 在存储器阵列中，多晶硅栅电极之间的间距是等效的并且具有更宽的间隔物宽度。 在逻辑器件区域中，多晶硅栅极之间的间距是不同的并且具有合适的间隔物宽度。 根据上述，通过在存储器阵列中使用分离的间隔物宽度，并且逻辑器件区域可以避免随后自对准自对准过程中位线与位线之间的泄漏路径。

公开(公告)号：US06469342B1

公开(公告)日：2002-10-22

申请号：US09990158

申请日：2001-11-20

申请人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Hung

发明人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Hung

IPC分类号： H01L29788

CPC分类号： H01L29/792 ,  H01L21/28282

摘要： A silicon nitride read-only memory that prevents the antenna effect is described. The structure of the silicon nitride read-only memory includes a word-line, an electron-trapping layer and a metal protection layer. The word line covers the substrate. The electron-trapping layer is positioned between the word line and the substrate. The metal protection line covers the substrate and electrically connects the word line to a grounding doped region in the substrate. Moreover, the resistance of the metal protection line is higher than that of the word line. The charges generated during the manufacturing process are conducted to the substrate through the metal protection line. The resistance of the metal protection line is also higher than that of the word line. The metal protection line can be burnt out by a high current after the completion of the manufacturing process to ensure a normal operation for the read-only memory.

摘要翻译： 描述了防止天线效应的氮化硅只读存储器。 氮化硅只读存储器的结构包括字线，电子捕获层和金属保护层。 字线覆盖基板。 电子捕获层位于字线和衬底之间。 金属保护线覆盖基板并将字线电连接到基板中的接地掺杂区域。 此外，金属保护线的电阻高于字线。 在制造过程中产生的电荷通过金属保护线进行到基板。 金属保护线的电阻也高于字线。 在完成制造过程之后，金属保护线可以被高电流烧毁，以确保只读存储器正常工作。

公开(公告)号：US07804122B2

公开(公告)日：2010-09-28

申请号：US12434828

申请日：2009-05-04

申请人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

发明人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

IPC分类号： H01L31/119

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7881 ,  H01L29/792

摘要： A non-volatile memory includes a substrate having two openings, a stacked gate structure disposed on the substrate between the two openings, a liner disposed on a bottom of each of the two openings and parts of a sidewall of each of the two openings, a second conductive layer disposed on the liner at the bottom of each of the two openings, and a third conductive layer on the second conductive layer and the liner. The stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, and a first conductive layer. The liner has a top surface lower than that of the substrate. The second conductive layer has a top surface co-planar with that of the liner. The third conductive layer has a top surface at least co-planar with that of the substrate and lower than that of the first dielectric layer.

摘要翻译： 非易失性存储器包括具有两个开口的衬底，设置在两个开口之间的衬底上的堆叠栅极结构，设置在两个开口中的每一个的底部和两个开口中的每一个的侧壁的一部分的衬垫， 设置在两个开口中的每一个的底部的衬垫上的第二导电层，以及在第二导电层和衬垫上的第三导电层。 层叠栅极结构包括第一介电层，电荷存储层，第二介电层和第一导电层。 衬垫具有比衬底更低的顶表面。 第二导电层具有与衬垫的顶表面共面的顶表面。 第三导电层具有至少与基底的共面的顶表面，并且低于第一介电层的顶表面。

公开(公告)号：US20080054322A1

公开(公告)日：2008-03-06

申请号：US11468311

申请日：2006-08-30

申请人： Chien-Hung Liu ,  Shou-Wei Huang ,  Ying-Tso Chen ,  Yu-Tsung Lin

发明人： Chien-Hung Liu ,  Shou-Wei Huang ,  Ying-Tso Chen ,  Yu-Tsung Lin

IPC分类号： H01L29/94

CPC分类号： H01L27/115 ,  H01L27/0207 ,  H01L27/11568

摘要： A memory is provided. The memory includes a substrate, a number of parallel bit lines, a number of parallel word lines and at least a oxide-nitride-oxide (ONO) structure. The bit lines are disposed in the substrate. The word lines are disposed on the substrate. The word lines are crossed with but not perpendicular to the bit lines. The ONO structure is disposed between the word lines and the substrate.

摘要翻译： 提供记忆。 存储器包括衬底，多个并行位线，多个并行字线和至少氧化物 - 氧化物 - 氧化物（ONO）结构。 位线设置在基板中。 字线设置在基板上。 字线与位线交叉但不垂直于位线。 ONO结构设置在字线和衬底之间。

公开(公告)号：US20090212353A1

公开(公告)日：2009-08-27

申请号：US12434828

申请日：2009-05-04

申请人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

发明人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7881 ,  H01L29/792

摘要： A non-volatile memory includes a substrate having two openings, a stacked gate structure disposed on the substrate between the two openings, a liner disposed on a bottom of each of the two openings and parts of a sidewall of each of the two openings, a second conductive layer disposed on the liner at the bottom of each of the two openings, and a third conductive layer on the second conductive layer and the liner. The stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, and a first conductive layer. The liner has a top surface lower than that of the substrate. The second conductive layer has a top surface co-planar with that of the liner. The third conductive layer has a top surface at least co-planar with that of the substrate and lower than that of the first dielectric layer.

摘要翻译： 非易失性存储器包括具有两个开口的衬底，设置在两个开口之间的衬底上的堆叠栅极结构，设置在两个开口中的每一个的底部和两个开口中的每一个的侧壁的一部分的衬垫， 设置在两个开口中的每一个的底部的衬垫上的第二导电层，以及在第二导电层和衬垫上的第三导电层。 层叠栅极结构包括第一介电层，电荷存储层，第二介电层和第一导电层。 衬垫具有比衬底更低的顶表面。 第二导电层具有与衬垫的顶表面共面的顶表面。 第三导电层具有至少与基底的共面的顶表面，并且低于第一介电层的顶表面。

公开(公告)号：US07572691B2

公开(公告)日：2009-08-11

申请号：US11435458

申请日：2006-05-16

申请人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

发明人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7881 ,  H01L29/792

摘要： A method of fabricating a non-volatile memory is provided. First, two openings are formed on a substrate. A stacked gate structure comprising a first dielectric layer, a charge storage layer, a second dielectric layer and a first conductive layer is formed on the substrate between the two openings. A liner is formed on a bottom and a portion of a sidewall of the tow openings, wherein a top surface of the liner is lower than that of the substrate. A second conductive layer is formed on the liner at the bottom of the two openings, wherein a top surface of the second conductive layer is co-planar with that of the liner. A third conductive layer is formed on the second conductive layer and the liner, wherein a top surface of the third conductive layer is co-planar with that of the substrate and lower than that of the first dielectric layer.

摘要翻译： 提供了一种制造非易失性存储器的方法。 首先，在基板上形成两个开口。 在两个开口之间的基板上形成包括第一电介质层，电荷存储层，第二电介质层和第一导电层的堆叠栅极结构。 衬套形成在丝束开口的侧壁的底部和一部分上，其中衬垫的顶表面低于衬底的顶表面。 第二导电层形成在两个开口的底部的衬垫上，其中第二导电层的顶表面与衬垫的顶表面共面。 第三导电层形成在第二导电层和衬垫上，其中第三导电层的顶表面与衬底的顶表面平行，并且低于第一介电层的顶表面。

公开(公告)号：US07608504B2

公开(公告)日：2009-10-27

申请号：US11468311

申请日：2006-08-30

申请人： Chien-Hung Liu ,  Shou-Wei Huang ,  Ying-Tso Chen ,  Yu-Tsung Lin

发明人： Chien-Hung Liu ,  Shou-Wei Huang ,  Ying-Tso Chen ,  Yu-Tsung Lin

IPC分类号： H01L21/00

CPC分类号： H01L27/115 ,  H01L27/0207 ,  H01L27/11568

摘要： A memory is provided. The memory includes a substrate, a number of parallel bit lines, a number of parallel word lines and at least a oxide-nitride-oxide (ONO) structure. The bit lines are disposed in the substrate. The word lines are disposed on the substrate. The word lines are crossed with but not perpendicular to the bit lines. The ONO structure is disposed between the word lines and the substrate.

摘要翻译： 提供记忆。 存储器包括衬底，多个并行位线，多个并行字线和至少氧化物 - 氧化物 - 氧化物（ONO）结构。 位线设置在基板中。 字线设置在基板上。 字线与位线交叉但不垂直于位线。 ONO结构设置在字线和衬底之间。