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    NON-VOLATILE MEMORY
    1.
    发明申请
    NON-VOLATILE MEMORY 有权
    非易失性存储器

    公开(公告)号：US20090212353A1

    公开(公告)日：2009-08-27

    申请号：US12434828

    申请日：2009-05-04

    申请人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

    发明人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

    IPC分类号： H01L29/792

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7881 ,  H01L29/792

    摘要： A non-volatile memory includes a substrate having two openings, a stacked gate structure disposed on the substrate between the two openings, a liner disposed on a bottom of each of the two openings and parts of a sidewall of each of the two openings, a second conductive layer disposed on the liner at the bottom of each of the two openings, and a third conductive layer on the second conductive layer and the liner. The stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, and a first conductive layer. The liner has a top surface lower than that of the substrate. The second conductive layer has a top surface co-planar with that of the liner. The third conductive layer has a top surface at least co-planar with that of the substrate and lower than that of the first dielectric layer.

    摘要翻译： 非易失性存储器包括具有两个开口的衬底，设置在两个开口之间的衬底上的堆叠栅极结构，设置在两个开口中的每一个的底部和两个开口中的每一个的侧壁的一部分的衬垫， 设置在两个开口中的每一个的底部的衬垫上的第二导电层，以及在第二导电层和衬垫上的第三导电层。 层叠栅极结构包括第一介电层，电荷存储层，第二介电层和第一导电层。 衬垫具有比衬底更低的顶表面。 第二导电层具有与衬垫的顶表面共面的顶表面。 第三导电层具有至少与基底的共面的顶表面，并且低于第一介电层的顶表面。

    Non-volatile memory and method of fabricating the same
    2.
    发明授权
    Non-volatile memory and method of fabricating the same 有权
    非易失性存储器及其制造方法

    公开(公告)号：US07572691B2

    公开(公告)日：2009-08-11

    申请号：US11435458

    申请日：2006-05-16

    申请人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

    发明人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

    IPC分类号： H01L21/336 ,  H01L21/8234

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7881 ,  H01L29/792

    摘要： A method of fabricating a non-volatile memory is provided. First, two openings are formed on a substrate. A stacked gate structure comprising a first dielectric layer, a charge storage layer, a second dielectric layer and a first conductive layer is formed on the substrate between the two openings. A liner is formed on a bottom and a portion of a sidewall of the tow openings, wherein a top surface of the liner is lower than that of the substrate. A second conductive layer is formed on the liner at the bottom of the two openings, wherein a top surface of the second conductive layer is co-planar with that of the liner. A third conductive layer is formed on the second conductive layer and the liner, wherein a top surface of the third conductive layer is co-planar with that of the substrate and lower than that of the first dielectric layer.

    摘要翻译： 提供了一种制造非易失性存储器的方法。 首先，在基板上形成两个开口。 在两个开口之间的基板上形成包括第一电介质层，电荷存储层，第二电介质层和第一导电层的堆叠栅极结构。 衬套形成在丝束开口的侧壁的底部和一部分上，其中衬垫的顶表面低于衬底的顶表面。 第二导电层形成在两个开口的底部的衬垫上，其中第二导电层的顶表面与衬垫的顶表面共面。 第三导电层形成在第二导电层和衬垫上，其中第三导电层的顶表面与衬底的顶表面平行，并且低于第一介电层的顶表面。

    Non-volatile memory and method of fabricating the same
    3.
    发明申请
    Non-volatile memory and method of fabricating the same 有权
    非易失性存储器及其制造方法

    公开(公告)号：US20070269943A1

    公开(公告)日：2007-11-22

    申请号：US11435458

    申请日：2006-05-16

    申请人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

    发明人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

    IPC分类号： H01L21/8234

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7881 ,  H01L29/792

    摘要： A method of fabricating a non-volatile memory is provided. First, two openings are formed on a substrate. A stacked gate structure comprising a first dielectric layer, a charge storage layer, a second dielectric layer and a first conductive layer is formed on the substrate between the two openings. A liner is formed on a bottom and a portion of a sidewall of the tow openings, wherein a top surface of the liner is lower than that of the substrate. A second conductive layer is formed on the liner at the bottom of the two openings, wherein a top surface of the second conductive layer is co-planar with that of the liner. A third conductive layer is formed on the second conductive layer and the liner, wherein a top surface of the third conductive layer is co-planar with that of the substrate and lower than that of the first dielectric layer.

    摘要翻译： 提供了一种制造非易失性存储器的方法。 首先，在基板上形成两个开口。 在两个开口之间的基板上形成包括第一电介质层，电荷存储层，第二电介质层和第一导电层的堆叠栅极结构。 衬套形成在丝束开口的侧壁的底部和一部分上，其中衬垫的顶表面低于衬底的顶表面。 第二导电层形成在两个开口的底部的衬垫上，其中第二导电层的顶表面与衬垫的顶表面共面。 第三导电层形成在第二导电层和衬垫上，其中第三导电层的顶表面与衬底的顶表面平行，并且低于第一介电层的顶表面。

    Non-volatile memory
    4.
    发明授权
    Non-volatile memory 有权
    非易失性存储器

    公开(公告)号：US07804122B2

    公开(公告)日：2010-09-28

    申请号：US12434828

    申请日：2009-05-04

    申请人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

    发明人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

    IPC分类号： H01L31/119

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7881 ,  H01L29/792

    摘要： A non-volatile memory includes a substrate having two openings, a stacked gate structure disposed on the substrate between the two openings, a liner disposed on a bottom of each of the two openings and parts of a sidewall of each of the two openings, a second conductive layer disposed on the liner at the bottom of each of the two openings, and a third conductive layer on the second conductive layer and the liner. The stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, and a first conductive layer. The liner has a top surface lower than that of the substrate. The second conductive layer has a top surface co-planar with that of the liner. The third conductive layer has a top surface at least co-planar with that of the substrate and lower than that of the first dielectric layer.

    摘要翻译： 非易失性存储器包括具有两个开口的衬底，设置在两个开口之间的衬底上的堆叠栅极结构，设置在两个开口中的每一个的底部和两个开口中的每一个的侧壁的一部分的衬垫， 设置在两个开口中的每一个的底部的衬垫上的第二导电层，以及在第二导电层和衬垫上的第三导电层。 层叠栅极结构包括第一介电层，电荷存储层，第二介电层和第一导电层。 衬垫具有比衬底更低的顶表面。 第二导电层具有与衬垫的顶表面共面的顶表面。 第三导电层具有至少与基底的共面的顶表面，并且低于第一介电层的顶表面。

    Method for evaluating failure rate
    5.
    发明授权
    Method for evaluating failure rate 有权
    评估失败率的方法

    公开(公告)号：US08510635B2

    公开(公告)日：2013-08-13

    申请号：US12979914

    申请日：2010-12-28

    申请人： Yun-Chi Yang ,  Yen-Song Liu ,  Chin-Hsien Chen ,  Sheng-Yu Wu ,  Kuan-Cheng Su

    发明人： Yun-Chi Yang ,  Yen-Song Liu ,  Chin-Hsien Chen ,  Sheng-Yu Wu ,  Kuan-Cheng Su

    IPC分类号： G11C29/00

    CPC分类号： G11C29/52 ,  G01R31/287 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56008 ,  G11C2029/0409 ,  G11C2029/0411

    摘要： A method for evaluating failure rate, which is applied to a plurality of semiconductor chips with error checking and correcting function includes the following steps. A first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of first failure bit counting values. The error checking and correcting function of each of the semiconductor chips is off. An aging test is applied to the semiconductor chips. A second read-write test operation as the first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of second failure bit counting values. The number of the semiconductor chips, the first failure bit counting values, the second failure bit counting values and an error checking and correcting coefficient are calculated to obtain a failure rate of the semiconductor chips.

    摘要翻译： 一种用于评估故障率的方法，其应用于具有错误检查和校正功能的多个半导体芯片包括以下步骤。 对半导体芯片应用第一读写测试操作，从而获得多个第一故障比特计数值。 每个半导体芯片的错误检查和校正功能关闭。 对半导体芯片进行老化试验。 作为第一读写测试操作的第二读写测试操作被应用于半导体芯片，从而获得多个第二故障位计数值。 计算半导体芯片的数量，第一故障比特计数值，第二故障比特计数值和错误校验系数，以获得半导体芯片的故障率。

    Fixing device and thermal module incorporating the same
    9.
    发明授权
    Fixing device and thermal module incorporating the same 有权
    固定装置和包含其的热模块

    公开(公告)号：US09076769B2

    公开(公告)日：2015-07-07

    申请号：US13467059

    申请日：2012-05-09

    申请人： Chin-Hsien Chen

    发明人： Chin-Hsien Chen

    IPC分类号： H05K7/20 ,  F28F7/00 ,  H05K7/00 ,  H01L23/467 ,  H01L23/40 ,  H01L23/427 ,  F28D15/02 ,  G06F1/20 ,  H01L23/367

    CPC分类号： H01L23/467 ,  F28D15/0275 ,  G06F1/20 ,  H01L23/367 ,  H01L23/4093 ,  H01L23/427 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An exemplary fixing device is for mounting a heat conduction plate to two electronic components. The fixing device includes a first mounting clip and a second mounting clip connected to the first mounting clip through arms. The first mounting clip includes a pressing plate pressing a first contacting portion of the heat conduction plate against one electronic component. The second mounting clip includes two pressing tabs pressing a second contacting portion of the heat conduction plate against the other electronic component. The pressing plate and the two pressing tabs are made of a single monolithic piece of material.

    摘要翻译： 示例性的固定装置用于将导热板安装到两个电子部件上。 固定装置包括第一安装夹和通过臂连接到第一安装夹的第二安装夹。 第一安装夹包括将导热板的第一接触部分压靠在一个电子部件上的按压板。 第二安装夹具包括将导热板的第二接触部分压靠在另一电子部件上的两个按压片。 按压板和两个按压片由单块整体材料制成。

    METHOD FOR EVALUATING FAILURE RATE
    10.
    发明申请
    METHOD FOR EVALUATING FAILURE RATE 有权
    评估失败率的方法

    公开(公告)号：US20120166130A1

    公开(公告)日：2012-06-28

    申请号：US12979914

    申请日：2010-12-28

    申请人： Yun-Chi YANG ,  Yen-Song Liu ,  Chin-Hsien Chen ,  Sheng-Yu Wu ,  Kuan-Cheng Su

    发明人： Yun-Chi YANG ,  Yen-Song Liu ,  Chin-Hsien Chen ,  Sheng-Yu Wu ,  Kuan-Cheng Su

    IPC分类号： G06F19/00

    CPC分类号： G11C29/52 ,  G01R31/287 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56008 ,  G11C2029/0409 ,  G11C2029/0411

    摘要： A method for evaluating failure rate, which is applied to a plurality of semiconductor chips with error checking and correcting function includes the following steps. A first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of first failure bit counting values. The error checking and correcting function of each of the semiconductor chips is off. An aging test is applied to the semiconductor chips. A second read-write test operation as the first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of second failure bit counting values. The number of the semiconductor chips, the first failure bit counting values, the second failure bit counting values and an error checking and correcting coefficient are calculated to obtain a failure rate of the semiconductor chips.

    摘要翻译： 一种用于评估故障率的方法，其应用于具有错误检查和校正功能的多个半导体芯片包括以下步骤。 对半导体芯片应用第一读写测试操作，从而获得多个第一故障比特计数值。 每个半导体芯片的错误检查和校正功能关闭。 对半导体芯片进行老化试验。 作为第一读写测试操作的第二读写测试操作被应用于半导体芯片，从而获得多个第二故障位计数值。 计算半导体芯片的数量，第一故障比特计数值，第二故障比特计数值和错误校验系数，以获得半导体芯片的故障率。