公开(公告)号：US06787416B2

公开(公告)日：2004-09-07

申请号：US10253039

申请日：2002-09-24

申请人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Hung

发明人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Hung

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： The present invention includes devices and methods to form non-volatile memory cells and peripheral devices, with reduced damage to the electron trapping layer and, optionally, reduced thermal exposure during CMOS processing. Particular aspects of the present invention are described in the claims, specification and drawings.

摘要翻译： 本发明包括用于形成非易失性存储器单元和外围设备的装置和方法，对电子俘获层的损害降低，并且可选地在CMOS处理期间减少热暴露。 在权利要求书，说明书和附图中描述了本发明的特定方面。

公开(公告)号：US06436800B1

公开(公告)日：2002-08-20

申请号：US09990393

申请日：2001-11-20

申请人： Tung-Cheng Kuo ,  Shou-Wei Hung ,  Chien-Hung Liu ,  Shyi-Shuh Pan

发明人： Tung-Cheng Kuo ,  Shou-Wei Hung ,  Chien-Hung Liu ,  Shyi-Shuh Pan

IPC分类号： H01L2138

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： A fabrication method for a nonvolatile memory with a shallow junction is described. A gate structure, comprising an electron-trapping layer and a conductive layer, is formed on a substrate. A doped spacer is formed on the sidewall of the gate structure. Buried bit lines are further formed in the substrate beside the gate structure. Thereafter, thermal process is conducted to diffuse the dopants from the doped spacer into the substrate adjacent to the buried bit lines.

摘要翻译： 描述了一种具有浅结的非易失性存储器的制造方法。 在基板上形成包括电子捕获层和导电层的栅极结构。 掺杂间隔物形成在栅极结构的侧壁上。 在栅极结构旁边的衬底中进一步形成掩埋位线。 此后，进行热处理以将掺杂的掺杂剂从埋入的位线扩散到衬底中。

公开(公告)号：US06469342B1

公开(公告)日：2002-10-22

申请号：US09990158

申请日：2001-11-20

申请人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Hung

发明人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Hung

IPC分类号： H01L29788

CPC分类号： H01L29/792 ,  H01L21/28282

摘要： A silicon nitride read-only memory that prevents the antenna effect is described. The structure of the silicon nitride read-only memory includes a word-line, an electron-trapping layer and a metal protection layer. The word line covers the substrate. The electron-trapping layer is positioned between the word line and the substrate. The metal protection line covers the substrate and electrically connects the word line to a grounding doped region in the substrate. Moreover, the resistance of the metal protection line is higher than that of the word line. The charges generated during the manufacturing process are conducted to the substrate through the metal protection line. The resistance of the metal protection line is also higher than that of the word line. The metal protection line can be burnt out by a high current after the completion of the manufacturing process to ensure a normal operation for the read-only memory.

摘要翻译： 描述了防止天线效应的氮化硅只读存储器。 氮化硅只读存储器的结构包括字线，电子捕获层和金属保护层。 字线覆盖基板。 电子捕获层位于字线和衬底之间。 金属保护线覆盖基板并将字线电连接到基板中的接地掺杂区域。 此外，金属保护线的电阻高于字线。 在制造过程中产生的电荷通过金属保护线进行到基板。 金属保护线的电阻也高于字线。 在完成制造过程之后，金属保护线可以被高电流烧毁，以确保只读存储器正常工作。

公开(公告)号：US06559010B1

公开(公告)日：2003-05-06

申请号：US10003320

申请日：2001-12-06

申请人： Tung-Cheng Kuo ,  Shou-Wei Hwang ,  Chien-Hung Liu ,  Shyi-Shuh Pan

发明人： Tung-Cheng Kuo ,  Shou-Wei Hwang ,  Chien-Hung Liu ,  Shyi-Shuh Pan

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： A method is described for forming a non-volatile memory comprising dividing a substrate into at least a memory array area and a logic device area. An oxide/nitride/oxide (ONO) layer is firstly formed on the substrate, and a photoresist layer is formed on the ONO layer by bit line photo process, and a bit line ion implantation process is performed on the substrate to form the plurality of bit lines structure. Then, a first polysilicon layer is deposited to form a plurality of word lines by word line photo condition. The complementary metal-oxide-semiconductor (CMOS) ONO layer is used to store the charge and the ONO layer is only touched by the photoresist layer once. Furthermore, the separated adjust photo condition of the memory array area and the logic device area can create a safe oxide thickness to solve the problem of leakage path between bit lines to bit lines by using a self-aligned silicide process.

摘要翻译： 描述了一种用于形成非易失性存储器的方法，包括将衬底划分成至少存储器阵列区域和逻辑器件区域。 首先在衬底上形成氧化物/氮化物/氧化物（ONO）层，并且通过位线光刻工艺在ONO层上形成光致抗蚀剂层，并在衬底上进行位线离子注入工艺以形成多个 位线结构。 然后，通过字线照片条件沉积第一多晶硅层以形成多个字线。 互补金属氧化物半导体（CMOS）ONO层用于存储电荷，并且ONO层仅被光致抗蚀剂层触及一次。 此外，存储器阵列区域和逻辑器件区域的分离的调整照相条件可以产生安全的氧化物厚度，以通过使用自对准硅化物处理来解决位线到位线之间的泄漏路径的问题。

公开(公告)号：US06818956B2

公开(公告)日：2004-11-16

申请号：US10643335

申请日：2003-08-15

申请人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

发明人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

IPC分类号： H01L2362

CPC分类号： H01L29/792 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L29/66833

摘要： A nonvolatile read-only memory device, wherein a word line is on a substrate and the word line includes a metal layer and a polysilicon line. A trapping layer is further located between the word line and the substrate. A polysilicon protection line is formed over the substrate and the polysilicon protection line connects the word line and a grounded doped region in the substrate, wherein the resistance of the polysilicon protection line is higher than that of the word line.

摘要翻译： 一种非易失性只读存储器件，其中字线在衬底上，字线包括金属层和多晶硅线。 捕获层还位于字线和基板之间。 多晶硅保护线形成在衬底上，多晶硅保护线连接字线和衬底中的接地掺杂区，其中多晶硅保护线的电阻高于字线的电阻。

公开(公告)号：US06680227B2

公开(公告)日：2004-01-20

申请号：US10134223

申请日：2002-04-25

申请人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

发明人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

IPC分类号： H01L218238

CPC分类号： H01L29/792 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L29/66833

摘要： A nonvolatile read-only memory device, wherein a word line is on a substrate and the word line includes a metal layer a polysilicon line. A trapping layer is further located between the word line and the substrate. A polysilicon protection line is formed over the substrate and the polysilicon protection line connects the word line and a grounded doped region in the substrate, wherein the resistance of the polysilicon protection line is higher than that of the word line.

公开(公告)号：US06876044B2

公开(公告)日：2005-04-05

申请号：US10680023

申请日：2003-10-06

申请人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

发明人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

IPC分类号： H01L21/8246 ,  H01L27/115 ,  H01L29/792 ,  H01L31/119

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792

摘要： An ultraviolet-programmable P-type Mask ROM is described. The threshold voltages of all memory cells are raised at first to make each memory cell to be in a first logic state, in which the channel is hard to switch on, in order to prevent a leakage current. After the bit lines and the word lines are formed, the Mask ROM is programmed by irradiating the substrate with UV light to inject electrons into the ONO layer under the openings to make the memory cells under the openings be in a second logic state.

摘要翻译： 描述了紫外线可编程P型掩模ROM。 首先提高所有存储器单元的阈值电压，以使每个存储器单元处于通道难以接通的第一逻辑状态，以防止漏电流。 在形成位线和字线之后，通过用UV光照射衬底来编程掩模ROM，以将电子注入到开口下面的ONO层中，以使开口下的存储单元处于第二逻辑状态。

公开(公告)号：US06812507B2

公开(公告)日：2004-11-02

申请号：US10636448

申请日：2003-08-06

申请人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

发明人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

IPC分类号： H01L27148

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  Y10S438/954

摘要： A non-volatile memory capable of preventing the antenna effect and the fabrication thereof are described. The non-volatile memory includes a word-line having a high resistance portion and a memory cell portion on a substrate and a charge trapping layer located between the word-line and the substrate. The high resistance portion is electrically connected with a grounding doped region in the substrate and the memory cell portion is electrically connected with a metal interconnect over the substrate.

摘要翻译： 描述能够防止天线效应及其制造的非易失性存储器。 非易失性存储器包括在基板上具有高电阻部分和存储单元部分的字线以及位于字线和基板之间的电荷捕获层。 高电阻部分与衬底中的接地掺杂区域电连接，并且存储单元部分与衬底上的金属互连电连接。

公开(公告)号：US06713315B2

公开(公告)日：2004-03-30

申请号：US10134270

申请日：2002-04-25

申请人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

发明人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

IPC分类号： H01L2100

CPC分类号： H01L27/11266 ,  H01L27/105 ,  H01L27/11293

摘要： A method for fabricating a Mask ROM is described, in which an ONO composite layer and a plurality of gate structures are formed on a substrate. A plurality of bit-lines are formed in the substrate between the gate structures and a plurality of word-lines are formed over the substrate to electrically connect with the gate structures. A chemical vapor deposition anti-reflective coating (CVD-ARC) with coding windows therein and an inter-layer dielectric layer are formed over the substrate. A coding process is then performed by using UV light to form a plurality of charged coding regions in the charge trapping layer not covered by the CVD-ARC. A plurality of plugs are then formed in the coding windows.

摘要翻译： 描述了一种用于制造掩模ROM的方法，其中在基板上形成ONO复合层和多个栅极结构。 在栅极结构之间的衬底中形成多个位线，并且在衬底上形成多个字线以与栅极结构电连接。 在其上形成了具有编码窗口的化学气相沉积抗反射涂层（CVD-ARC）和层间电介质层。 然后通过使用UV光在未被CVD-ARC覆盖的电荷捕获层中形成多个带电编码区域来进行编码处理。 然后在编码窗口中形成多个插头。

公开(公告)号：US06642113B1

公开(公告)日：2003-11-04

申请号：US10128742

申请日：2002-04-23

申请人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

发明人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

IPC分类号： H01L2100

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  Y10S438/954

摘要： A non-volatile memory capable of preventing the antenna effect and the fabrication thereof are described. The non-volatile memory includes a word-line having a high resistance portion and a memory cell portion on a substrate and a charge trapping layer located between the word-line and the substrate. The high resistance portion is electrically connected with a grounding doped region in the substrate and the memory cell portion is electrically connected with a metal interconnect over the substrate.

摘要翻译： 描述能够防止天线效应及其制造的非易失性存储器。 非易失性存储器包括在基板上具有高电阻部分和存储单元部分的字线以及位于字线和基板之间的电荷捕获层。 高电阻部分与衬底中的接地掺杂区域电连接，并且存储单元部分与衬底上的金属互连电连接。