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39 条记录 (耗时 0.033 秒)

    Hardware demapping of TLBs shared by multiple threads
    21.
    发明申请
    Hardware demapping of TLBs shared by multiple threads 有权
    由多个线程共享的TLB的硬件解映射

    公开(公告)号：US20070061547A1

    公开(公告)日：2007-03-15

    申请号：US11222577

    申请日：2005-09-09

    申请人： Paul Jordan ,  Manish Shah ,  Gregory Grohoski

    发明人： Paul Jordan ,  Manish Shah ,  Gregory Grohoski

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1054 ,  G06F12/1027 ,  G06F12/109 ,  G06F2212/656 ,  G06F2212/682 ,  G06F2212/683

    摘要： In one embodiment, a processor comprising at least one translation lookaside buffer (TLB) and a control unit coupled to the TLB. The control unit is configured to track whether or not at least one update to the TLB is pending for at least one of a plurality of strands. Each strand comprises hardware to support a different thread of a plurality of concurrently activateable threads in the processor. The strands share the TLB, and the control unit is configured to delay a demap operation issued from one of the estrands responsive to the pending update, if any.

    摘要翻译： 在一个实施例中，处理器包括至少一个翻译后备缓冲器（TLB）和耦合到该TLB的控制单元。 控制单元被配置为跟踪针对多个线段中的至少一个的至少一个对TLB的更新是否待决。 每条链包括用于支持处理器中多个可同时激活的线程的不同线程的硬件。 链路共享TLB，并且控制单元被配置为响应于待决更新（如果有的话）延迟从一个estrand发出的解映射操作。

    System and method for shared decoding using a data replay scheme
    22.
    发明授权
    System and method for shared decoding using a data replay scheme 有权
    使用数据重放方案进行共享解码的系统和方法

    公开(公告)号：US07167531B2

    公开(公告)日：2007-01-23

    申请号：US09954777

    申请日：2001-09-17

    申请人： Mark Greenberg ,  Manish Shah

    发明人： Mark Greenberg ,  Manish Shah

    IPC分类号： H03D1/00

    CPC分类号： H04L1/0068 ,  H03M13/00 ,  H04L1/0054 ,  H04N21/2383 ,  H04N21/4382

    摘要： A system and method are described in which a decoder decodes data from a plurality of data streams. In one embodiment, the decoder is restored to the state it was in the last time it processed data from each data stream by re-decoding data stored in a replay buffer before decoding new data from each respective data stream. In one embodiment, multiple decoders are grouped together to process data from a plurality of satellite transponders.

    摘要翻译： 描述了一种系统和方法，其中解码器解码来自多个数据流的数据。 在一个实施例中，解码器恢复到在最后一次处理来自每个数据流的数据的状态下，通过在从每个相应数据流解码新数据之前重新解码存储在重放缓冲器中的数据。 在一个实施例中，多个解码器被分组在一起以处理来自多个卫星转发器的数据。

    Jig for guiding placement of femoral component of the implant in knee replacement surgery
    24.
    发明授权
    Jig for guiding placement of femoral component of the implant in knee replacement surgery 有权

    公开(公告)号：US11622776B2

    公开(公告)日：2023-04-11

    申请号：US17239350

    申请日：2021-04-23

    申请人： Manish Shah

    发明人： Manish Shah

    IPC分类号： A61B17/15 ,  A61F2/38 ,  A61F2/46 ,  A61F2/30

    摘要： The present jig for guiding placement of femoral component of the implant in a knee replacement surgery (J) is a pre-assembled Jig (J) which ensures precision fit femoral implant for knee replacement based on difference of cuts in millimeters instead of the usual angle measurement in degrees. It avoids intrusion of the intramedullary canal substantially decreasing the risks of embolism. It enables the surgeon to use precise values of depth of cuts obtained from a system for obtaining optimum fit implant as described in patent application number 3896/MUM2015. This enables the surgeon to control precisely the placement of the implant in terms of flexion or extension, varus or valgus, internal or external rotation It also enables precise placement of the fourin-one cutting block simultaneously with the distal femur cut; ensuring precise placement of knee femoral component of the knee implant. This reduces efforts and time taken during the surgery.

    DATA SOURCE ATTRIBUTION SYSTEM
    26.
    发明申请
    DATA SOURCE ATTRIBUTION SYSTEM 有权
    数据源引导系统

    公开(公告)号：US20100088313A1

    公开(公告)日：2010-04-08

    申请号：US12554306

    申请日：2009-09-04

    申请人： Auren Hoffman ,  Manish Shah ,  Jeremy Lizt ,  Vivek Sodera

    发明人： Auren Hoffman ,  Manish Shah ,  Jeremy Lizt ,  Vivek Sodera

    IPC分类号： G06F17/30

    CPC分类号： G06F17/30867 ,  G06F17/30312 ,  G06F17/30528 ,  G06F17/3053 ,  G06F17/30876 ,  G06Q50/01 ,  H04L67/306

    摘要： A data attribution system uses a unique identifier (UID) that uniquely identifies a particular individual. A search is conducted of different data sources and, different types of profile information associated with the UID is extracted from the data sources. The different types of profile information associated with the same UID is aggregated together and displayed in a same screen presentation on a user interface.

    摘要翻译： 数据归属系统使用唯一标识特定个体的唯一标识符（UID）。 对不同的数据源进行搜索，并从数据源中提取与UID相关联的不同类型的简档信息。 与相同UID相关联的不同类型的简档信息被聚合在一起，并在用户界面上以相同的屏幕显示显示。

    DECODING MULTITHREADED INSTRUCTIONS
    27.
    发明申请
    DECODING MULTITHREADED INSTRUCTIONS 有权
    解码多项指令

    公开(公告)号：US20100011190A1

    公开(公告)日：2010-01-14

    申请号：US12170144

    申请日：2008-07-09

    申请人： Robert Golla ,  Manish Shah

    发明人： Robert Golla ,  Manish Shah

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3017 ,  G06F9/26 ,  G06F9/30145 ,  G06F9/3851

    摘要： A microprocessor capable of decoding a plurality of instructions associated with a plurality of threads is disclosed. The microprocessor may comprise a first array comprising a first plurality of microcode operations associated with an instruction from within the plurality, the first array capable of delivering a first predetermined number of microcode operations from the first plurality of microcode operations. The microprocessor may further comprise a second array comprising a second plurality of microcode operations, the second array capable of providing one or more of the second plurality of microcode operations in the event that the instruction decodes into more than the first predetermined number of microcode operations. The microprocessor may further comprise an arbiter coupled between the first and second arrays, where the arbiter may determine which thread from the plurality of threads accesses the second array.

    摘要翻译： 公开了能够解码与多个线程相关联的多个指令的微处理器。 微处理器可以包括第一阵列，其包括与来自多个内的指令相关联的第一多个微代码操作，第一阵列能够从第一多个微代码操作传送第一预定数量的微代码操作。 微处理器还可以包括包括第二多个微代码操作的第二阵列，所述第二阵列能够在所述指令解码成多于所述第一预定数量的微代码操作的情况下能够提供所述第二多个微代码操作中的一个或多个。 微处理器还可以包括耦合在第一和第二阵列之间的仲裁器，其中仲裁器可以确定来自多个线程的线程访问第二阵列。

    Demapping TLBs across physical cores of a chip
    29.
    发明申请
    Demapping TLBs across physical cores of a chip 有权
    跨TLB跨芯片的物理内核

    公开(公告)号：US20070061548A1

    公开(公告)日：2007-03-15

    申请号：US11222614

    申请日：2005-09-09

    申请人： Paul Jordan ,  Manish Shah ,  Gregory Grohoski

    发明人： Paul Jordan ,  Manish Shah ,  Gregory Grohoski

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1027 ,  G06F2212/682 ,  G06F2212/683

    摘要： In one embodiment, a processor comprises a plurality of processor cores and an interconnect to which the plurality of processor cores are coupled. Each of the plurality of processor cores comprises at least one translation lookaside buffer (TLB). A first processor core is configured to broadcast a demap command on the interconnect responsive to executing a demap operation. The demap command identifies one or more translations to be invalidated in the TLBs, and remaining processor cores are configured to invalidate the translations in the respective TLBs. The remaining processor cores transmit a response to the first processor core, and the first processor core is configured to delay continued processing subsequent to the demap operation until the responses are received from each of the remaining processor cores.

    摘要翻译： 在一个实施例中，处理器包括多个处理器核和多个处理器核耦合到的互连。 多个处理器核心中的每一个包括至少一个平移后备缓冲器（TLB）。 第一处理器核心被配置为响应于执行解映射操作而在互连上广播解映射命令。 解映射命令标识在TLB中将被无效的一个或多个翻译，并且剩余的处理器核被配置为使相应TLB中的翻译无效。 剩余的处理器核心向第一处理器核心发送响应，并且第一处理器核心被配置为延迟解映射操作之后的持续处理，直到从每个其余处理器核心接收到响应。

    Automatic array quality analysis
    30.
    发明申请
    Automatic array quality analysis 审中-公开
    自动阵列质量分析

    公开(公告)号：US20060282221A1

    公开(公告)日：2006-12-14

    申请号：US11148626

    申请日：2005-06-09

    申请人： Manish Shah ,  James Gruneisen ,  Luc Vincent

    发明人： Manish Shah ,  James Gruneisen ,  Luc Vincent

    IPC分类号： G06F19/00 ,  G06K9/00

    CPC分类号： G06K9/00127 ,  G16B25/00

    摘要： Systems, methods and computer readable media for automatically inspecting a chemical array. At least one processor is adapted to receive a digitized image of the chemical array, and at least one of hardware, software and firmware are adapted to quantify at least one visual characteristic of a feature on the chemical array that contributes to uniformity of the visualization of the feature. Systems, methods and computer readable media are provided for automatically quantifying a visual characteristic of a chemical array. A digitized image of a chemical array having at least one feature is received, and at least one visual characteristic of a feature on the chemical array that contributes to uniformity of the visualization of the feature automatically quantified. A result based on the automatically quantification processing may be outputted to quantify at least one visual characteristic of a feature.

    摘要翻译： 用于自动检查化学数组的系统，方法和计算机可读介质。 至少一个处理器适于接收化学阵列的数字化图像，并且硬件，软件和固件中的至少一个适于量化化学阵列上的特征的至少一个视觉特征，其有助于可视化的均匀性 的功能。 提供了系统，方法和计算机可读介质，用于自动量化化学阵列的视觉特性。 接收具有至少一个特征的化学阵列的数字化图像，并且化学阵列上的特征的至少一个视觉特征有助于自动量化特征的可视化的一致性。 可以输出基于自动量化处理的结果来量化特征的至少一个视觉特征。