公开(公告)号：US20130320437A1

公开(公告)日：2013-12-05

申请号：US13615044

申请日：2012-09-13

申请人： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Po-Chih Su ,  Ruey-Hsin Liu

发明人： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Po-Chih Su ,  Ruey-Hsin Liu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66734 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823493 ,  H01L27/0922 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/7803 ,  H01L29/7813

摘要： A device includes a trench extending into a semiconductor region and having a first conductivity type, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer and having an edge portion overlapping the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion contacting the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type. A MOS-containing device is at a surface of the semiconductor region.

公开(公告)号：US20130320432A1

公开(公告)日：2013-12-05

申请号：US13588893

申请日：2012-08-17

申请人： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Po-Chih Su ,  Ruey-Hsin Liu

发明人： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Po-Chih Su ,  Ruey-Hsin Liu

IPC分类号： H01L27/088

CPC分类号： H01L21/823487 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/82385 ,  H01L21/823885 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66666 ,  H01L29/66712

摘要： A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a space, and are electrically interconnected. The space between the first and the second gate electrodes overlaps the doped semiconductor region. The device further includes a MOS containing device.

公开(公告)号：US09450056B2

公开(公告)日：2016-09-20

申请号：US13351295

申请日：2012-01-17

申请人： Chun-Wai Ng ,  Ruey-Hsin Liu ,  Jun Cai ,  Hsueh-Liang Chou ,  Chi-Chih Chen

发明人： Chun-Wai Ng ,  Ruey-Hsin Liu ,  Jun Cai ,  Hsueh-Liang Chou ,  Chi-Chih Chen

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06

CPC分类号： H01L29/7816 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368

摘要： An LDMOS transistor with a dummy gate comprises an extended drift region formed over a substrate, a drain region formed in the extended drift region, a channel region formed in the extended drift region, a source region formed in the channel region and a dielectric layer formed over the extended drift region. The LDMOS transistor with a dummy gate further comprises an active gate formed over the channel region and a dummy gate formed over the extended drift region. The dummy gate helps to reduce the gate charge of the LDMOS transistor while maintaining the breakdown voltage of the LDMOS transistor.

摘要翻译： 具有伪栅极的LDMOS晶体管包括形成在衬底上的扩展漂移区，形成在扩展漂移区中的漏极区，形成在扩展漂移区中的沟道区，形成在沟道区中的源极区和形成的电介质层 在扩展漂移区域上。 具有伪栅极的LDMOS晶体管还包括形成在沟道区上的有源栅极和形成在扩展漂移区上的伪栅极。 虚拟栅极有助于降低LDMOS晶体管的栅极电荷，同时保持LDMOS晶体管的击穿电压。

公开(公告)号：US20130181285A1

公开(公告)日：2013-07-18

申请号：US13351295

申请日：2012-01-17

申请人： Chun-Wai Ng ,  Ruey-Hsin Liu ,  Jun Cai ,  Hsueh-Liang Chou ,  Chi-Chih Chen

发明人： Chun-Wai Ng ,  Ruey-Hsin Liu ,  Jun Cai ,  Hsueh-Liang Chou ,  Chi-Chih Chen

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368

摘要： An LDMOS transistor with a dummy gate comprises an extended drift region formed over a substrate, a drain region formed in the extended drift region, a channel region formed in the extended drift region, a source region formed in the channel region and a dielectric layer formed over the extended drift region. The LDMOS transistor with a dummy gate further comprises an active gate formed over the channel region and a dummy gate formed over the extended drift region. The dummy gate helps to reduce the gate charge of the LDMOS transistor while maintaining the breakdown voltage of the LDMOS transistor.

摘要翻译： 具有伪栅极的LDMOS晶体管包括形成在衬底上的扩展漂移区，形成在扩展漂移区中的漏极区，形成在扩展漂移区中的沟道区，形成在沟道区中的源极区和形成的电介质层 在扩展漂移区域上。 具有伪栅极的LDMOS晶体管还包括形成在沟道区上的有源栅极和形成在扩展漂移区上的伪栅极。 虚拟栅极有助于降低LDMOS晶体管的栅极电荷，同时保持LDMOS晶体管的击穿电压。

公开(公告)号：US08461647B2

公开(公告)日：2013-06-11

申请号：US12721045

申请日：2010-03-10

申请人： Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Hsiao-Chin Tuan

发明人： Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Hsiao-Chin Tuan

IPC分类号： H01L29/66

CPC分类号： H01L29/42368 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device is provided that, in an embodiment, is in the form of a high voltage MOS (HVMOS) device. The device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. The gate structure includes a gate dielectric which has a first portion with a first thickness and a second portion with a second thickness. The second thickness is greater than the first thickness. A gate electrode is disposed on the first and second portion. In an embodiment, a drift region underlies the second portion of the gate dielectric. A method of fabricating the same is also provided.

摘要翻译： 提供了一种半导体器件，其在一个实施例中是高压MOS（HVMOS）器件的形式。 该器件包括形成在半导体衬底上的半导体衬底和栅极结构。 栅极结构包括具有第一厚度的第一部分和具有第二厚度的第二部分的栅极电介质。 第二厚度大于第一厚度。 栅电极设置在第一和第二部分上。 在一个实施例中，漂移区域位于栅极电介质的第二部分的下方。 还提供了一种制造该方法的方法。

公开(公告)号：US08507988B2

公开(公告)日：2013-08-13

申请号：US12792055

申请日：2010-06-02

申请人： Chih-Wen Yao ,  Robert S. J. Pan ,  Ruey-Hsin Liu ,  Hsueh-Liang Chou ,  Puo-Yu Chiang ,  Chi-Chih Chen ,  Hsiao Chin Tuan

发明人： Chih-Wen Yao ,  Robert S. J. Pan ,  Ruey-Hsin Liu ,  Hsueh-Liang Chou ,  Puo-Yu Chiang ,  Chi-Chih Chen ,  Hsiao Chin Tuan

IPC分类号： H01L29/66

CPC分类号： H01L29/7816 ,  H01L29/086 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66689

摘要： A high voltage (HV) device includes a gate dielectric structure over a substrate. The gate dielectric structure has a first portion and a second portion. The first portion has a first thickness and is over a first well region of a first dopant type in the substrate. The second portion has a second thickness and is over a second well region of a second dopant type. The first thickness is larger than the second thickness. A gate electrode is disposed over the gate dielectric structure. A metallic layer is over and coupled with the gate electrode. The metallic layer extends along a direction of a channel under the gate dielectric structure. At least one source/drain (S/D) region is disposed within the first well region of the first dopant type.

摘要翻译： 高压（HV）器件包括在衬底上的栅极电介质结构。 栅介质结构具有第一部分和第二部分。 第一部分具有第一厚度并且在衬底中超过第一掺杂剂类型的第一阱区域。 第二部分具有第二厚度并且在第二掺杂剂类型的第二阱区之上。 第一厚度大于第二厚度。 栅电极设置在栅介电结构上。 一个金属层结合在栅电极上。 金属层沿栅极电介质结构下方的沟道的方向延伸。 至少一个源极/漏极（S / D）区域设置在第一掺杂剂类型的第一阱区域内。

公开(公告)号：US20110220995A1

公开(公告)日：2011-09-15

申请号：US12721045

申请日：2010-03-10

申请人： Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Hsiao-Chin Tuan

发明人： Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Chih-Wen Yao ,  Hsiao-Chin Tuan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/42368 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device is provided that, in an embodiment, is in the form of a high voltage MOS (HVMOS) device. The device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. The gate structure includes a gate dielectric which has a first portion with a first thickness and a second portion with a second thickness. The second thickness is greater than the first thickness. A gate electrode is disposed on the first and second portion. In an embodiment, a drift region underlies the second portion of the gate dielectric. A method of fabricating the same is also provided.

摘要翻译： 提供了一种半导体器件，其在一个实施例中是高压MOS（HVMOS）器件的形式。 该器件包括形成在半导体衬底上的半导体衬底和栅极结构。 栅极结构包括具有第一厚度的第一部分和具有第二厚度的第二部分的栅极电介质。 第二厚度大于第一厚度。 栅电极设置在第一和第二部分上。 在一个实施例中，漂移区域位于栅极电介质的第二部分的下方。 还提供了一种制造该方法的方法。

公开(公告)号：US20080211026A1

公开(公告)日：2008-09-04

申请号：US11594508

申请日：2006-11-08

申请人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

发明人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

IPC分类号： H01L23/62

CPC分类号： H01L29/66477 ,  H01L21/28 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66128 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/8611

摘要： A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

摘要翻译： 半导体结构包括衬底，覆盖衬底的第一导电类型的第一阱区，覆盖衬底的与第一导电类型相反的第二导电类型的第二阱区，与第一阱和第二阱相邻的衬垫区 区域，在所述第一阱区域的一部分中并且从所述第一阱区域的顶表面延伸到所述第一阱区域中的绝缘区域;从所述第一阱区域延伸到所述第二阱区域的栅极电介质，其中所述栅极 电介质具有绝缘区域上的一部分，以及栅极电介质上的栅电极。

公开(公告)号：US08592923B2

公开(公告)日：2013-11-26

申请号：US13280035

申请日：2011-10-24

申请人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

发明人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

IPC分类号： H01L29/66

CPC分类号： H01L29/66477 ,  H01L21/28 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66128 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/8611

摘要： A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

公开(公告)号：US20110006366A1

公开(公告)日：2011-01-13

申请号：US12887300

申请日：2010-09-21

申请人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

发明人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

IPC分类号： H01L29/78

CPC分类号： H01L29/66477 ,  H01L21/28 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66128 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/8611

摘要： A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

摘要翻译： 半导体结构包括衬底，覆盖衬底的第一导电类型的第一阱区，覆盖衬底的与第一导电类型相反的第二导电类型的第二阱区，与第一阱和第二阱相邻的衬垫区 区域，在所述第一阱区域的一部分中并且从所述第一阱区域的顶表面延伸到所述第一阱区域中的绝缘区域;从所述第一阱区域延伸到所述第二阱区域的栅极电介质，其中所述栅极 电介质具有绝缘区域上的一部分，以及栅极电介质上的栅电极。