公开(公告)号：US09450056B2

公开(公告)日：2016-09-20

申请号：US13351295

申请日：2012-01-17

申请人： Chun-Wai Ng ,  Ruey-Hsin Liu ,  Jun Cai ,  Hsueh-Liang Chou ,  Chi-Chih Chen

发明人： Chun-Wai Ng ,  Ruey-Hsin Liu ,  Jun Cai ,  Hsueh-Liang Chou ,  Chi-Chih Chen

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06

CPC分类号： H01L29/7816 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368

摘要： An LDMOS transistor with a dummy gate comprises an extended drift region formed over a substrate, a drain region formed in the extended drift region, a channel region formed in the extended drift region, a source region formed in the channel region and a dielectric layer formed over the extended drift region. The LDMOS transistor with a dummy gate further comprises an active gate formed over the channel region and a dummy gate formed over the extended drift region. The dummy gate helps to reduce the gate charge of the LDMOS transistor while maintaining the breakdown voltage of the LDMOS transistor.

摘要翻译： 具有伪栅极的LDMOS晶体管包括形成在衬底上的扩展漂移区，形成在扩展漂移区中的漏极区，形成在扩展漂移区中的沟道区，形成在沟道区中的源极区和形成的电介质层 在扩展漂移区域上。 具有伪栅极的LDMOS晶体管还包括形成在沟道区上的有源栅极和形成在扩展漂移区上的伪栅极。 虚拟栅极有助于降低LDMOS晶体管的栅极电荷，同时保持LDMOS晶体管的击穿电压。

公开(公告)号：US20130181285A1

公开(公告)日：2013-07-18

申请号：US13351295

申请日：2012-01-17

申请人： Chun-Wai Ng ,  Ruey-Hsin Liu ,  Jun Cai ,  Hsueh-Liang Chou ,  Chi-Chih Chen

发明人： Chun-Wai Ng ,  Ruey-Hsin Liu ,  Jun Cai ,  Hsueh-Liang Chou ,  Chi-Chih Chen

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368

摘要： An LDMOS transistor with a dummy gate comprises an extended drift region formed over a substrate, a drain region formed in the extended drift region, a channel region formed in the extended drift region, a source region formed in the channel region and a dielectric layer formed over the extended drift region. The LDMOS transistor with a dummy gate further comprises an active gate formed over the channel region and a dummy gate formed over the extended drift region. The dummy gate helps to reduce the gate charge of the LDMOS transistor while maintaining the breakdown voltage of the LDMOS transistor.

摘要翻译： 具有伪栅极的LDMOS晶体管包括形成在衬底上的扩展漂移区，形成在扩展漂移区中的漏极区，形成在扩展漂移区中的沟道区，形成在沟道区中的源极区和形成的电介质层 在扩展漂移区域上。 具有伪栅极的LDMOS晶体管还包括形成在沟道区上的有源栅极和形成在扩展漂移区上的伪栅极。 虚拟栅极有助于降低LDMOS晶体管的栅极电荷，同时保持LDMOS晶体管的击穿电压。

公开(公告)号：US08507988B2

公开(公告)日：2013-08-13

申请号：US12792055

申请日：2010-06-02

申请人： Chih-Wen Yao ,  Robert S. J. Pan ,  Ruey-Hsin Liu ,  Hsueh-Liang Chou ,  Puo-Yu Chiang ,  Chi-Chih Chen ,  Hsiao Chin Tuan

发明人： Chih-Wen Yao ,  Robert S. J. Pan ,  Ruey-Hsin Liu ,  Hsueh-Liang Chou ,  Puo-Yu Chiang ,  Chi-Chih Chen ,  Hsiao Chin Tuan

IPC分类号： H01L29/66

CPC分类号： H01L29/7816 ,  H01L29/086 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66689

摘要： A high voltage (HV) device includes a gate dielectric structure over a substrate. The gate dielectric structure has a first portion and a second portion. The first portion has a first thickness and is over a first well region of a first dopant type in the substrate. The second portion has a second thickness and is over a second well region of a second dopant type. The first thickness is larger than the second thickness. A gate electrode is disposed over the gate dielectric structure. A metallic layer is over and coupled with the gate electrode. The metallic layer extends along a direction of a channel under the gate dielectric structure. At least one source/drain (S/D) region is disposed within the first well region of the first dopant type.

摘要翻译： 高压（HV）器件包括在衬底上的栅极电介质结构。 栅介质结构具有第一部分和第二部分。 第一部分具有第一厚度并且在衬底中超过第一掺杂剂类型的第一阱区域。 第二部分具有第二厚度并且在第二掺杂剂类型的第二阱区之上。 第一厚度大于第二厚度。 栅电极设置在栅介电结构上。 一个金属层结合在栅电极上。 金属层沿栅极电介质结构下方的沟道的方向延伸。 至少一个源极/漏极（S / D）区域设置在第一掺杂剂类型的第一阱区域内。

公开(公告)号：US20080237703A1

公开(公告)日：2008-10-02

申请号：US11692213

申请日：2007-03-28

申请人： Yi-Chun Lin ,  Chi-Chih Chen ,  Kuo-Ming Wu ,  Ruey-Hsin Liu

发明人： Yi-Chun Lin ,  Chi-Chih Chen ,  Kuo-Ming Wu ,  Ruey-Hsin Liu

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7835

摘要： An exemplary embodiment of a semiconductor device capable of high-voltage operation includes a substrate with a well region therein. A gate stack with a first side and a second side opposite thereto, overlies the well region. Within the well region, a doped body region includes a channel region extending under a portion of the gate stack and a drift region is adjacent to the channel region. A drain region is within the drift region and spaced apart by a distance from the first side thereof and a source region is within the doped body region near the second side thereof. There is no P-N junction between the doped body region and the well region.

摘要翻译： 能够进行高压操作的半导体器件的示例性实施例包括其中具有阱区的衬底。 具有与其相对的第一侧和第二侧的栅极堆叠覆盖在阱区域上。 在阱区内，掺杂体区域包括在栅叠层的一部分下延伸的沟道区，漂移区与沟道区相邻。 漏极区域在漂移区域内并与其第一侧隔开距离，并且源极区域在其第二侧附近的掺杂体区域内。 在掺杂体区和阱区之间不存在P-N结。

公开(公告)号：US07602037B2

公开(公告)日：2009-10-13

申请号：US11692213

申请日：2007-03-28

申请人： Yi-Chun Lin ,  Chi-Chih Chen ,  Kuo-Ming Wu ,  Ruey-Hsin Liu

发明人： Yi-Chun Lin ,  Chi-Chih Chen ,  Kuo-Ming Wu ,  Ruey-Hsin Liu

IPC分类号： H01L27/088 ,  H01L29/06

CPC分类号： H01L29/7816 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7835

摘要： An exemplary embodiment of a semiconductor device capable of high-voltage operation includes a substrate with a well region therein. A gate stack with a first side and a second side opposite thereto, overlies the well region. Within the well region, a doped body region includes a channel region extending under a portion of the gate stack and a drift region is adjacent to the channel region. A drain region is within the drift region and spaced apart by a distance from the first side thereof and a source region is within the doped body region near the second side thereof. There is no P-N junction between the doped body region and the well region.

摘要翻译： 能够进行高压操作的半导体器件的示例性实施例包括其中具有阱区的衬底。 具有与其相对的第一侧和第二侧的栅极堆叠覆盖在阱区域上。 在阱区内，掺杂体区域包括在栅叠层的一部分下延伸的沟道区，漂移区与沟道区相邻。 漏极区域在漂移区域内并与其第一侧隔开距离，并且源极区域在其第二侧附近的掺杂体区域内。 在掺杂体区和阱区之间不存在P-N结。

公开(公告)号：US20130049108A1

公开(公告)日：2013-02-28

申请号：US13219283

申请日：2011-08-26

申请人： Chi-Chih Chen ,  Kun-Hsuan Tien ,  Ruey-Hsin Liu

发明人： Chi-Chih Chen ,  Kun-Hsuan Tien ,  Ruey-Hsin Liu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7809 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66734

摘要： A MOSFET includes a semiconductor substrate having a top surface, a body region of a first conductivity type in the semiconductor substrate, and a double diffused drain (DDD) region having a top surface lower than a bottom surface of the body region. The DDD region is of a second conductivity type opposite the first conductivity type. The MOSFET further includes a gate oxide, and a gate electrode separated from the body region by the gate oxide. A portion of the gate oxide and a portion of the gate electrode are below the top surface of the body region.

摘要翻译： MOSFET包括半导体衬底，其具有顶表面，在半导体衬底中具有第一导电类型的主体区域，以及具有比主体区域的底表面低的顶表面的双扩散漏极（DDD）区域。 DDD区域是与第一导电类型相反的第二导电类型。 MOSFET还包括栅极氧化物和通过栅极氧化物与体区分离的栅电极。 栅极氧化物的一部分和栅电极的一部分在身体区域的顶表面下方。

公开(公告)号：US09818859B2

公开(公告)日：2017-11-14

申请号：US13219283

申请日：2011-08-26

申请人： Chi-Chih Chen ,  Kun-Hsuan Tien ,  Ruey-Hsin Liu

发明人： Chi-Chih Chen ,  Kun-Hsuan Tien ,  Ruey-Hsin Liu

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/08

CPC分类号： H01L29/7809 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66734

摘要： A MOSFET includes a semiconductor substrate having a top surface, a body region of a first conductivity type in the semiconductor substrate, and a double diffused drain (DDD) region having a top surface lower than a bottom surface of the body region. The DDD region is of a second conductivity type opposite the first conductivity type. The MOSFET further includes a gate oxide, and a gate electrode separated from the body region by the gate oxide. A portion of the gate oxide and a portion of the gate electrode are below the top surface of the body region.

公开(公告)号：US20080191276A1

公开(公告)日：2008-08-14

申请号：US11703678

申请日：2007-02-08

申请人： Chi-Chih Chen ,  Yi-Chun Lin ,  Kuo-Ming Wu ,  Ruey-Hsin Liu

发明人： Chi-Chih Chen ,  Yi-Chun Lin ,  Kuo-Ming Wu ,  Ruey-Hsin Liu

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/66689 ,  H01L21/26586 ,  H01L29/7816

摘要： Semiconductor devices and fabrication methods thereof. The semiconductor device includes a semiconductor substrate with a body region of a first doping type. A gate structure is patterned on the semiconductor substrate. A single spacer is formed on a first sidewall of the gate structure. A body region of a first doping type is formed in the semiconductor substrate adjacent to a second sidewall of the gate structure. A source region of a second doping type is formed on the body region and having an edge aligned with the second sidewall of the gate structure. A drain region of the second doping type is formed on the semiconductor substrate and having an edge aligned with an exterior surface of the single sidewall.

摘要翻译： 半导体器件及其制造方法。 半导体器件包括具有第一掺杂类型的体区的半导体衬底。 在半导体衬底上构图栅极结构。 在栅极结构的第一侧壁上形成单个间隔物。 第一掺杂类型的体区形成在与栅极结构的第二侧壁相邻的半导体衬底中。 第二掺杂类型的源极区域形成在主体区域上并且具有与栅极结构的第二侧壁对准的边缘。 第二掺杂类型的漏极区域形成在半导体衬底上并且具有与单个侧壁的外表面对准的边缘。

公开(公告)号：US20060022866A1

公开(公告)日：2006-02-02

申请号：US10968472

申请日：2004-10-19

申请人： Eric Walton ,  Chi-Chih Chen

发明人： Eric Walton ,  Chi-Chih Chen

IPC分类号： G01S13/93 ,  G01S7/28

CPC分类号： G01S7/352 ,  G01S3/48 ,  G01S5/04 ,  G01S13/003 ,  G01S13/32 ,  G01S13/46 ,  G01S13/931 ,  G01S2007/358 ,  G01S2007/4086 ,  G01S2013/0245 ,  G01S2013/0254 ,  G01S2013/9332 ,  G01S2013/9375 ,  G01S2013/9385 ,  G01S2013/9389 ,  H01Q1/3233 ,  H01Q1/3283 ,  H01Q9/0407 ,  H01Q21/08 ,  H01Q23/00

摘要： The present invention is a radar system for detecting the presence of obstacles. The radar system includes at least one transmitting antenna and at least one receiving antenna. The transmitting antenna receives an input signal and transmits an electromagnetic wave. The electromagnetic wave reflects off an obstacle back to the receiving antenna. The receiving antenna captures the reflected electromagnetic wave and produces an output signal. The output signal is then combined with the local reference signal in a quadrature mixer. The resulting in-phase (I) and quadrature (Q) signals may be further processed and then transmitted to a processing system. The processing system uses a suitable algorithm, e.g., a back projection algorithm, to estimate the type and location of obstacles that reflected the electromagnetic wave. In an exemplary embodiment, the algorithm is adapted to discriminate between different sizes and locations of obstacles in order to determine if there is a hazard. Based on this information, the processing system then communicates with a visual and/or audible warning system in order to alert the driver about the obstacle if it has been determined to be a hazard.

摘要翻译： 本发明是用于检测障碍物的存在的雷达系统。 雷达系统包括至少一个发射天线和至少一个接收天线。 发送天线接收输入信号并发送电磁波。 电磁波从障碍物反射回接收天线。 接收天线捕获反射的电磁波并产生输出信号。 然后将输出信号与正交混频器中的本地参考信号组合。 可以进一步处理所得到的同相（I）和正交（Q）信号，然后将其发送到处理系统。 处理系统使用合适的算法，例如反投影算法来估计反映电磁波的障碍物的类型和位置。 在示例性实施例中，该算法适于区分障碍物的不同大小和位置，以便确定是否存在危险。 基于该信息，处理系统然后与视觉和/或听觉警报系统进行通信，以便如果已被确定为危险，则警告驾驶员关于障碍物。

公开(公告)号：US20110169682A1

公开(公告)日：2011-07-14

申请号：US13059371

申请日：2009-10-09

申请人： Chi-Chih Chen

发明人： Chi-Chih Chen

IPC分类号： G01S13/88

CPC分类号： G01S7/025 ,  G01S13/003 ,  G01S13/0209 ,  G01S13/34 ,  G01S13/885

摘要： A forward-looking radar system adapted to detect and identify buried or near surface objects from a moving ground vehicle has been developed. The system incorporates a radar detection system and in one embodiment is mounted on a ground vehicle. The system is adapted to differentiate common roadway clutter from objects of interest.

摘要翻译： 已经开发了适用于从移动地面车辆中检测和识别掩埋或近表面物体的前瞻性雷达系统。 该系统包括雷达检测系统，并且在一个实施例中安装在地面车辆上。 该系统适用于将常见的道路杂波与感兴趣的物体区分开来。