公开(公告)号：US20080211026A1

公开(公告)日：2008-09-04

申请号：US11594508

申请日：2006-11-08

申请人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

发明人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

IPC分类号： H01L23/62

CPC分类号： H01L29/66477 ,  H01L21/28 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66128 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/8611

摘要： A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

摘要翻译： 半导体结构包括衬底，覆盖衬底的第一导电类型的第一阱区，覆盖衬底的与第一导电类型相反的第二导电类型的第二阱区，与第一阱和第二阱相邻的衬垫区 区域，在所述第一阱区域的一部分中并且从所述第一阱区域的顶表面延伸到所述第一阱区域中的绝缘区域;从所述第一阱区域延伸到所述第二阱区域的栅极电介质，其中所述栅极 电介质具有绝缘区域上的一部分，以及栅极电介质上的栅电极。

公开(公告)号：US06958546B2

公开(公告)日：2005-10-25

申请号：US10437373

申请日：2003-05-13

申请人： Fu-Jier Fan ,  Cheng-Yu Chu ,  Kuo Wei Lin ,  Shih-Jang Lin ,  Yang-Tung Fran ,  Chiou-Shian Peng

发明人： Fu-Jier Fan ,  Cheng-Yu Chu ,  Kuo Wei Lin ,  Shih-Jang Lin ,  Yang-Tung Fran ,  Chiou-Shian Peng

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/48

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A new method and processing sequence is provided for the formation of solder bumps that are in contact with underlying aluminum contact pads. A patterned layer of negative photoresist is interposed between a patterned layer of PE Si3N4 and a patterned layer of polyamide insulator. The patterned negative photoresist partially overlays the aluminum contact pad and prevents contact between the layer of polyamide insulator and the aluminum contact pad. By forming this barrier no moisture that is contained in the polyamide insulator can come in contact with the aluminum contact pad, therefore no corrosion in the surface of the aluminum contact pad can occur.

摘要翻译： 提供了一种新的方法和处理顺序，用于形成与下面的铝接触焊盘接触的焊料凸块。 负型光致抗蚀剂的图案化层插入在PE 3 N 4 N 4的图案化层和聚酰胺绝缘体的图案化层之间。 图案化的负光致抗蚀剂部分覆盖铝接触垫，并防止聚酰胺绝缘体层与铝接触垫之间的接触。 通过形成该屏障，聚酰胺绝缘体中所含的水分不能与铝接触垫接触，因此铝接触垫的表面中不会发生腐蚀。

公开(公告)号：US06876049B2

公开(公告)日：2005-04-05

申请号：US10272136

申请日：2002-10-16

申请人： Yang-Tung Fan ,  Chiou-Shian Peng ,  Cheng-Yu Chu ,  Shih-Jane Lin ,  Yen-Ming Chen ,  Fu-Jier Fan ,  Kuo-Wei Lin

发明人： Yang-Tung Fan ,  Chiou-Shian Peng ,  Cheng-Yu Chu ,  Shih-Jane Lin ,  Yen-Ming Chen ,  Fu-Jier Fan ,  Kuo-Wei Lin

IPC分类号： G02F1/1335 ,  H01L21/00 ,  H01L27/146 ,  H01L31/0216 ,  H01L31/0232

CPC分类号： H01L27/14685 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14645 ,  H01L31/02162 ,  H01L31/02327

摘要： Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon. A transparent encapsulant is deposited to planarize the color filter layer and completes the solid-state color image-forming device without conventional convex microlenses.

公开(公告)号：US06649507B1

公开(公告)日：2003-11-18

申请号：US09883163

申请日：2001-06-18

申请人： Yen-Ming Chen ,  Cheng-Yu Chu ,  Kuo-Wei Lin ,  Chiou-Shian Peng ,  Yang-Tung Fan ,  Fu-Jier Fan ,  Shih-Jane Lin

发明人： Yen-Ming Chen ,  Cheng-Yu Chu ,  Kuo-Wei Lin ,  Chiou-Shian Peng ,  Yang-Tung Fan ,  Fu-Jier Fan ,  Shih-Jane Lin

IPC分类号： H01L2144

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01083

摘要： A method of forming a bump structure, comprising the following steps. A structure having an exposed first conductive structure is provided. A first photoresist layer is formed over the structure and the exposed first conductive structure. A second capping photoresist layer is formed over the first photoresist layer. The first and second photoresist layers being comprised of different photoresist materials. The first and second photoresist layers are patterned to form an opening through the first and second photoresist layers and over the first conductive structure. The second capping photoresist layer prevents excessive formation of first photoresist layer residue during processing. A second conductive structure is formed within the opening. The first and second patterned photoresist layers are stripped. The second conductive structure is reflowed to form the bump structure.

摘要翻译： 一种形成凸块结构的方法，包括以下步骤。 提供具有暴露的第一导电结构的结构。 在结构和暴露的第一导电结构上形成第一光致抗蚀剂层。 在第一光致抗蚀剂层上形成第二覆盖光致抗蚀剂层。 第一和第二光致抗蚀剂层由不同的光致抗蚀剂材料组成。 图案化第一和第二光致抗蚀剂层以形成穿过第一和第二光致抗蚀剂层并在第一导电结构上的开口。 第二覆盖光致抗蚀剂层防止在处理期间过度形成第一光致抗蚀剂层残留物。 在开口内形成第二导电结构。 剥离第一和第二图案化的光致抗蚀剂层。 第二导电结构被回流以形成凸块结构。

公开(公告)号：US06605524B1

公开(公告)日：2003-08-12

申请号：US09950227

申请日：2001-09-10

申请人： Yang-Tung Fan ,  Cheng-Yu Chu ,  Fu-Jier Fan ,  Shih-Jane Lin ,  Chiou-Shian Peng ,  Yen-Ming Chen ,  Kuo-Wei Lin

发明人： Yang-Tung Fan ,  Cheng-Yu Chu ,  Fu-Jier Fan ,  Shih-Jane Lin ,  Chiou-Shian Peng ,  Yen-Ming Chen ,  Kuo-Wei Lin

IPC分类号： H01L2144

CPC分类号： H01L24/11 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/1191 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00014 ,  H01L2924/013

摘要： A new process is provided which is an extension and improvement of present processing for the creation of a solder bump. After the layers of Under Bump Metal and a layer of solder metal have been created in patterned and etched format and overlying the contact pad, following a conventional processing sequence, a layer of polyimide is deposited. The solder flow is performed using the thickness of the deposited layer of polyimide to control the height of the column underneath the reflown solder.

摘要翻译： 提供了一种新的工艺，其是用于产生焊料凸块的当前处理的延伸和改进。 在图形化和蚀刻形式下形成了凹凸金属层和焊料金属层之后，按照传统的处理顺序，沉积了一层聚酰亚胺。 使用聚酰亚胺沉积层的厚度来进行焊料流动，以控制在重熔焊料下面的柱的高度。

公开(公告)号：US06426281B1

公开(公告)日：2002-07-30

申请号：US09759911

申请日：2001-01-16

申请人： Kuo-Wei Lin ,  Cheng-Yu Chu ,  Yen-Ming Chen ,  Yang-Tung Fan ,  Fu-Jier Fan ,  Chiou-Shian Peng ,  Shih-Jang Lin

发明人： Kuo-Wei Lin ,  Cheng-Yu Chu ,  Yen-Ming Chen ,  Yang-Tung Fan ,  Fu-Jier Fan ,  Chiou-Shian Peng ,  Shih-Jang Lin

IPC分类号： H01L2144

CPC分类号： H01L24/12 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2224/05552

摘要： A new method and processing sequence is provided for the creation of interconnect bumps. A layer of passivation is deposited over a contact pad and patterned, creating an opening in the layer of passivation that aligns with the contact pad. A layer of UBM metal is deposited over the layer of passivation, the layer of UBM is overlying the contact pad and limited to the immediate surroundings of the contact pad. The central surface of the layer of UBM is selectively electroplated after which a layer of solder or solder alloy is solder printed over the electroplated surface of the layer of UBM. A solder flux or paste is applied over the surface of the solder printed solder compound or solder alloy. Flowing of the solder or solder alloy creates the solder bump of the invention.

公开(公告)号：US08592923B2

公开(公告)日：2013-11-26

申请号：US13280035

申请日：2011-10-24

申请人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

发明人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

IPC分类号： H01L29/66

CPC分类号： H01L29/66477 ,  H01L21/28 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66128 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/8611

摘要： A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

公开(公告)号：US20110006366A1

公开(公告)日：2011-01-13

申请号：US12887300

申请日：2010-09-21

申请人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

发明人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

IPC分类号： H01L29/78

CPC分类号： H01L29/66477 ,  H01L21/28 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66128 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/8611

摘要： A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

摘要翻译： 半导体结构包括衬底，覆盖衬底的第一导电类型的第一阱区，覆盖衬底的与第一导电类型相反的第二导电类型的第二阱区，与第一阱和第二阱相邻的衬垫区 区域，在所述第一阱区域的一部分中并且从所述第一阱区域的顶表面延伸到所述第一阱区域中的绝缘区域;从所述第一阱区域延伸到所述第二阱区域的栅极电介质，其中所述栅极 电介质具有绝缘区域上的一部分，以及栅极电介质上的栅电极。

公开(公告)号：US07816214B2

公开(公告)日：2010-10-19

申请号：US12362307

申请日：2009-01-29

申请人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

发明人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

IPC分类号： H01L21/8234

CPC分类号： H01L29/66477 ,  H01L21/28 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66128 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/8611

摘要： A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

摘要翻译： 半导体结构包括衬底，覆盖衬底的第一导电类型的第一阱区，覆盖衬底的与第一导电类型相反的第二导电类型的第二阱区，与第一阱和第二阱相邻的衬垫区 区域，在所述第一阱区域的一部分中并且从所述第一阱区域的顶表面延伸到所述第一阱区域中的绝缘区域;从所述第一阱区域延伸到所述第二阱区域的栅极电介质，其中所述栅极 电介质具有绝缘区域上的一部分，以及栅极电介质上的栅电极。

公开(公告)号：US07816169B2

公开(公告)日：2010-10-19

申请号：US12347468

申请日：2008-12-31

申请人： Yang-Tung Fan ,  Chiou-Shian Peng ,  Cheng-Yu Chu ,  Shih-Jane Lin ,  Yen-Ming Chen ,  Fu-Jier Fan ,  Kuo-Wei Li

发明人： Yang-Tung Fan ,  Chiou-Shian Peng ,  Cheng-Yu Chu ,  Shih-Jane Lin ,  Yen-Ming Chen ,  Fu-Jier Fan ,  Kuo-Wei Li

IPC分类号： H01L21/00

CPC分类号： H01L27/14685 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14645 ,  H01L31/02162 ,  H01L31/02327

摘要： Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon. A transparent encapsulant is deposited to planarize the color filter layer and completes the solid-state color image-forming device without conventional convex microlenses.

摘要翻译： 公开了一种有序的微电子制造顺序，其中滤色器通过直角沉积直接形成在CCD，CID或CMOS成像装置的光电检测器阵列上以形成凹入像素表面，并且覆盖有高透光率平面化膜 指定的折射率和物理性质，其优化光收集到光电二极管而不需要额外的常规微透镜。 光学平坦的顶表面用于封装和保护成像器免受化学和热清洁处理损伤，最小化形成的底层变化，其将形成在非平面表面上的图像的像差或引起反射损失，并且消除在切割期间引起的残留颗粒夹杂物， 打包。 通过在半导体衬底上光刻地构图光电二极管平面阵列来形成CCD成像器。 光电二极管阵列设置有金属遮光罩，钝化，并且在其上形成滤色器。 沉积透明密封剂以平坦化滤色器层并完成固态彩色图像形成装置，而不需要常规的凸起的微透镜。