公开(公告)号：US20130092986A1

公开(公告)日：2013-04-18

申请号：US13395608

申请日：2011-10-17

申请人： Wenwu Wang ,  Chao Zhao ,  Kai Han ,  Dapeng Chen

发明人： Wenwu Wang ,  Chao Zhao ,  Kai Han ,  Dapeng Chen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/82345 ,  H01L21/28114 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

摘要： A semiconductor device and a method for manufacturing the same, the method comprising: providing a semiconductor substrate; forming a dummy gate area on the substrate, forming spacers on sidewalls of the gate area, and forming source and drain areas in the semiconductor substrate on both sides of the dummy gate area, the dummy gate area comprising an interface layer and a dummy gate electrode; forming a dielectric cap layer on the dummy gate area and source and drain areas; planarizing the device with the dielectric cap layer on the source and drain areas as a stop layer; further removing the dummy gate electrode to expose the interface layer; and forming replacement gate area on the interface layer. The thickness of the gate groove may be controlled by the thickness of the dielectric cap layer, and the replacement gates of desired thickness and width may be further formed upon requirements. Thus, the aspect ratio of the gate groove is reduced and a sufficient low gate resistance is ensured.

摘要翻译： 一种半导体器件及其制造方法，所述方法包括：提供半导体衬底; 在所述基板上形成虚拟栅极区域，在所述栅极区域的侧壁上形成间隔物，以及在所述伪栅极区域的两侧形成所述半导体基板中的源极和漏极区域，所述伪栅极区域包括界面层和虚拟栅极电极 ; 在虚拟栅极区域和源极和漏极区域上形成电介质盖层; 使源极和漏极区域上的电介质盖层平坦化作为停止层; 进一步去除虚拟栅电极以露出界面层; 并在界面层上形成替换栅区。 栅极沟槽的厚度可以通过电介质盖层的厚度来控制，并且可以根据需要进一步形成所需厚度和宽度的替换栅极。 因此，栅极沟槽的纵横比减小，并且确保了足够的低栅极电阻。

公开(公告)号：US20130045588A1

公开(公告)日：2013-02-21

申请号：US13509551

申请日：2011-12-05

申请人： Huicai Zhong ,  Jun Luo ,  Chao Zhao ,  Qingqing Liang

发明人： Huicai Zhong ,  Jun Luo ,  Chao Zhao ,  Qingqing Liang

IPC分类号： H01L21/20

CPC分类号： H01L29/6653 ,  H01L29/78

摘要： A method for manufacturing a semiconductor device is disclosed, comprising: providing a substrate, a gate region on the substrate and a semiconductor region at both sides of the gate region; forming sacrificial spacers, which cover a portion of the semiconductor region, on sidewalls of the gate region; forming a metal layer on a portion of the semiconductor region outside the sacrificial spacers and on the gate region; removing the sacrificial spacers; performing annealing so that the metal layer reacts with the semiconductor region to form a metal-semiconductor compound layer on the semiconductor region; and removing unreacted metal layer. By separating the metal layer from the channel and the gate region of the device with the thickness of the sacrificial spacers, the effect of metal layer diffusion on the channel and the gate region is reduced and performance of the device is improved.

摘要翻译： 公开了一种制造半导体器件的方法，包括：提供衬底，衬底上的栅极区域和栅极区两侧的半导体区域; 在所述栅极区域的侧壁上形成覆盖所述半导体区域的一部分的牺牲间隔物; 在牺牲间隔物外部和栅极区域上的半导体区域的一部分上形成金属层; 去除牺牲隔离物; 进行退火，使得金属层与半导体区域反应，以在半导体区域上形成金属 - 半导体化合物层; 并除去未反应的金属层。 通过将金属层与器件的栅极区域与牺牲间隔物的厚度分开，金属层扩散对沟道和栅极区域的影响降低，并且器件的性能得到改善。

公开(公告)号：US20120261803A1

公开(公告)日：2012-10-18

申请号：US13394935

申请日：2011-10-17

申请人： Wenwu Wang ,  Chao Zhao ,  Kai Han ,  Dapeng Chen

发明人： Wenwu Wang ,  Chao Zhao ,  Kai Han ,  Dapeng Chen

IPC分类号： H01L21/31 ,  H01L29/02

CPC分类号： C23C14/08 ,  C23C14/5806 ,  C23C16/401 ,  C23C16/56

摘要： The present invention forms Hf1-xSixOy having a cubic phase or a tetragonal phase by doping a specific amount of SiO2 component into the high-K gate dielectric material HfO2 in combination with an optimized thermal processing technique, to thereby acquire a high-K gate dielectric thin film material having a greater bandgap, a higher K value and high thermal stability. Besides, the high-K gate dielectric thin film and a preparation method thereof proposed in the present invention are helpful to solve the problem of crystallization of ultra-thin films.

摘要翻译： 本发明通过与优化的热处理技术结合，将特定量的SiO 2成分掺入到高K栅介质材料HfO 2中，形成具有立方相或四方相的Hf1-xSixOy，从而获得高K栅极电介质 具有较大带隙，较高K值和高热稳定性的薄膜材料。 此外，本发明中提出的高K栅介质薄膜及其制备方法有助于解决超薄膜结晶的问题。

公开(公告)号：US20120080792A1

公开(公告)日：2012-04-05

申请号：US13143507

申请日：2011-02-17

申请人： Chao Zhao

发明人： Chao Zhao

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76873 ,  H01L21/76885 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a method for forming a metal interlayer via, comprising: forming a seed layer on a first dielectric layer and a first metal layer embedded in the first dielectric layer; forming a mask pattern on the seed layer to expose a portion of the seed layer covering some of the first metal layer; growing a second metal layer on the exposed portion of the seed layer; removing the mask pattern and a portion of the seed layer carrying the mask pattern to expose side walls of the second metal layer, a portion of the first metal layer and the first dielectric layer; forming an insulating barrier layer on the side walls, the portion of the first metal layer and the first dielectric layer. There is also provided a method for forming a metal interconnection line. Both of them can suppress the occurrence of voids. There is further provided a metal interconnection structure comprising a contact plug, a via and a metal interconnection line, wherein the via is formed on the metal interconnection line, the metal gate and/or the contact plug.

摘要翻译： 提供一种用于形成金属中间层通孔的方法，包括：在第一电介质层上形成晶种层和嵌入第一介电层中的第一金属层; 在种子层上形成掩模图案以暴露覆盖一些第一金属层的种子层的一部分; 在种子层的暴露部分上生长第二金属层; 去除掩模图案和携带掩模图案的种子层的一部分以暴露第二金属层的侧壁，第一金属层和第一介电层的一部分; 在侧壁上形成绝缘阻挡层，第一金属层和第一介电层的部分。 还提供了一种用于形成金属互连线的方法。 他们都可以抑制空洞的发生。 还提供了一种金属互连结构，其包括接触插塞，通孔和金属互连线，其中通孔形成在金属互连线，金属栅极和/或接触插塞上。

公开(公告)号：US09419108B2

公开(公告)日：2016-08-16

申请号：US14406904

申请日：2012-08-17

申请人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu ,  Chao Zhao ,  Tianchun Ye

发明人： Qingqing Liang ,  Huicai Zhong ,  Huilong Zhu ,  Chao Zhao ,  Tianchun Ye

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/785 ,  H01L29/7855

摘要： One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor substrate and removing parts of the substrates situated on two sides of the gate stack; forming sidewall spacers on sidewalls of the gate stack and on sidewalls of the part of the substrate under the gate stack; forming doped regions in parts of the substrate on two sides of the gate stack, and forming a first dielectric layer to cover the entire semiconductor structure; selectively removing parts of the gate stack and parts of the first dielectric layer to form a channel region opening and source/drain region openings; forming a high K dielectric layer on sidewalls of the channel region opening; and implementing epitaxy process to form a continuous fin structure that spans across the channel region opening and the source/drain region openings.

摘要翻译： 本发明的一个实施例提供了一种用于制造半导体结构的方法，其包括：在半导体衬底上形成栅极叠层并去除位于栅极叠层两侧的衬底的部分; 在所述栅极堆叠的侧壁上以及在所述栅极堆叠下的所述衬底的所述部分的侧壁上形成侧壁间隔物; 在所述栅极堆叠的两侧上在所述衬底的部分中形成掺杂区域，以及形成覆盖整个半导体结构的第一介电层; 选择性地去除所述栅极堆叠的部分和所述第一介电层的部分以形成沟道区域开口和源极/漏极区域开口; 在沟道区域开口的侧壁上形成高K电介质层; 并且实现外延工艺以形成跨越沟道区域开口和源极/漏极区域开口的连续翅片结构。

公开(公告)号：US20150236134A1

公开(公告)日：2015-08-20

申请号：US14412237

申请日：2012-07-18

申请人： Huicai Zhong ,  Qingqing Liang ,  Chao Zhao

发明人： Huicai Zhong ,  Qingqing Liang ,  Chao Zhao

IPC分类号： H01L29/66

CPC分类号： H01L29/66795 ,  H01L21/268 ,  H01L21/76283 ,  H01L29/665 ,  H01L29/785

摘要： A method of manufacturing a FinFET semiconductor device is provided, wherein the semiconductor fins are formed in a parallel arrangement which intersects the gates arranged in parallel. The polycrystalline silicon layer is deposited and then converted into a single crystal silicon layer such that the single crystal silicon layer and the semiconductor fins are integrated in essence, i.e., the source/drain region in the semiconductor fins is raised and the top area of the semiconductor fins is extended. Subsequently, the single crystal silicon layer above the top of the semiconductor fins is converted into a metal silicide so as to form a source/drain region contact. The source/drain region contact in the present invention has a larger area than that in a conventional FinFET, which decreases the contact resistance and facilitates the formation of a self-aligned metal plug in the follow-up process.

摘要翻译： 提供一种制造FinFET半导体器件的方法，其中半导体鳍片形成为与并行布置的栅极相交的平行布置。 沉积多晶硅层，然后转换为单晶硅层，使得单晶硅层和半导体鳍片本质上是集成的，即半导体鳍片中的源极/漏极区域被升高，并且顶部区域 半导体鳍片延伸。 随后，将半导体鳍片顶部上方的单晶硅层转换为金属硅化物，以形成源极/漏极区域接触。 本发明中的源极/漏极区域的接触面积大于传统的FinFET的面积，这在以后的过程中降低了接触电阻并且有利于形成自对准的金属插塞。

公开(公告)号：US08748983B2

公开(公告)日：2014-06-10

申请号：US13380828

申请日：2011-08-12

申请人： Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

发明人： Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

IPC分类号： H01L27/12 ,  H01L21/70

CPC分类号： H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： An embedded source/drain MOS transistor and a formation method thereof are provided. The embedded source/drain MOS transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source/drain stack embedded in the semiconductor substrate at both sides of the gate structure with an upper surface of the source/drain stack being exposed, wherein the source/drain stack comprises a dielectric layer and a semiconductor layer above the dielectric layer. The present invention can cut off the path for the leakage current from the source region and the drain region to the semiconductor substrate, thereby reducing the leakage current from the source region and the drain region to the semiconductor substrate.

摘要翻译： 提供一种嵌入式源极/漏极MOS晶体管及其形成方法。 嵌入式源极/漏极MOS晶体管包括：半导体衬底; 半导体衬底上的栅极结构; 以及在源极/漏极叠层的上表面被暴露的栅极结构的两侧嵌入在半导体衬底中的源极/漏极堆叠，其中源极/漏极叠层包括电介质层和介电层上方的半导体层。 本发明可以切断从源极区域和漏极区域到半导体衬底的漏电流的路径，从而减少从源极区域和漏极区域到半导体衬底的漏电流。

公开(公告)号：US08685851B2

公开(公告)日：2014-04-01

申请号：US13139063

申请日：2011-01-27

申请人： Chao Zhao ,  Wenwu Wang

发明人： Chao Zhao ,  Wenwu Wang

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L27/101 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/53238 ,  H01L27/2436 ,  H01L29/78 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  H01L2924/0002 ,  H01L2924/00

摘要： A manufacturing method of a MOS device with memory function is provided, which includes: providing a semiconductor substrate, a surface of the semiconductor substrate being covered by a first dielectric layer, a metal interconnect structure being formed in the first dielectric layer; forming a second dielectric layer overlying a surface of the first dielectric layer and the metal interconnect structure; forming an opening in the second dielectric layer, a bottom of the opening revealing the metal interconnect structure; forming an alloy layer at the bottom of the opening, material of the alloy layer containing copper and other metal; and performing a thermal treatment to the alloy layer and the metal interconnect structure to form, on the surface of the metal interconnect structure, a compound layer containing oxygen element. The compound layer containing oxygen element and the MOS device formed in the semiconductor substrate constitute a MOS device with memory function. The method provides a processing which has high controllability and improves the performance of devices.

摘要翻译： 提供具有记忆功能的MOS器件的制造方法，其包括：提供半导体衬底，半导体衬底的表面被第一介电层覆盖，金属互连结构形成在第一介电层中; 形成覆盖在所述第一电介质层和所述金属互连结构的表面上的第二电介质层; 在所述第二介电层中形成开口，所述开口的底部露出所述金属互连结构; 在开口的底部形成合金层，含有铜等金属的合金层的材料; 对合金层和金属互连结构进行热处理，在金属互连结构的表面形成含有氧元素的化合物层。 包含氧元素的化合物层和形成在半导体衬底中的MOS器件构成具有记忆功能的MOS器件。 该方法提供了具有高可控性和提高设备性能的处理。

公开(公告)号：US08575019B2

公开(公告)日：2013-11-05

申请号：US13143507

申请日：2011-02-17

申请人： Chao Zhao

发明人： Chao Zhao

IPC分类号： H01L23/535

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76873 ,  H01L21/76885 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a method for forming a metal interlayer via, comprising: forming a seed layer on a first dielectric layer and a first metal layer embedded in the first dielectric layer; forming a mask pattern on the seed layer to expose a portion of the seed layer covering some of the first metal layer; growing a second metal layer on the exposed portion of the seed layer; removing the mask pattern and a portion of the seed layer carrying the mask pattern to expose side walls of the second metal layer, a portion of the first metal layer and the first dielectric layer; forming an insulating barrier layer on the side walls, the portion of the first metal layer and the first dielectric layer. There is also provided a method for forming a metal interconnection line. Both of them can suppress the occurrence of voids. There is further provided a metal interconnection structure comprising a contact plug, a via and a metal interconnection line, wherein the via is formed on the metal interconnection line, the metal gate and/or the contact plug.

摘要翻译： 提供一种用于形成金属中间层通孔的方法，包括：在第一电介质层上形成晶种层和嵌入第一介电层中的第一金属层; 在种子层上形成掩模图案以暴露覆盖一些第一金属层的种子层的一部分; 在种子层的暴露部分上生长第二金属层; 去除掩模图案和承载掩模图案的种子层的一部分以暴露第二金属层的侧壁，第一金属层和第一介电层的一部分; 在侧壁上形成绝缘阻挡层，第一金属层和第一介电层的部分。 还提供了一种用于形成金属互连线的方法。 他们都可以抑制空洞的发生。 还提供了一种金属互连结构，其包括接触插塞，通孔和金属互连线，其中通孔形成在金属互连线，金属栅极和/或接触插塞上。

公开(公告)号：US20130249012A1

公开(公告)日：2013-09-26

申请号：US13640733

申请日：2012-04-11

申请人： Qiuxia Xu ,  Chao Zhao ,  Gaobo Xu

发明人： Qiuxia Xu ,  Chao Zhao ,  Gaobo Xu

IPC分类号： H01L27/092 ,  H01L21/265

CPC分类号： H04L21/02 ,  H01L21/265 ,  H01L21/823807 ,  H01L29/7833 ,  H01L29/7843

摘要： This invention discloses a CMOS device, which includes: a first MOSFET; a second MOSFET different from the type of the first MOSFET; a first stressed layer covering the first MOSFET and having a first stress; and a second stressed layer covering the second MOSFET, wherein the second stressed layer is doped with ions, and thus has a second stress different from the first stress. This invention's CMOS device and method for manufacturing the same make use of a partitioned ion implantation method to realize a dual stress liner, without the need of removing the tensile stressed layer on the PMOS region or the compressive stressed layer on the NMOS region by photolithography/etching, thus simplifying the process and reducing the cost, and at the same time, preventing the stress in the liner on the NMOS region or PMOS region from the damage that might be caused by the thermal process of the deposition process.

摘要翻译： 本发明公开了一种CMOS器件，其包括：第一MOSFET; 与第一MOSFET的类型不同的第二MOSFET; 覆盖所述第一MOSFET并具有第一应力的第一应力层; 以及覆盖所述第二MOSFET的第二应力层，其中所述第二应力层掺杂有离子，并且因此具有不同于所述第一应力的第二应力。 本发明的CMOS器件及其制造方法利用分离离子注入方法实现双重应力衬垫，而不需要通过光刻/光刻技术去除PMOS区域上的拉伸应力层或NMOS区域上的压应力层， 蚀刻，从而简化了工艺并降低了成本，并且同时防止了NMOS区域或PMOS区域上的衬垫中的应力不受由沉积工艺的热处理引起的损伤。