公开(公告)号：US08802518B2

公开(公告)日：2014-08-12

申请号：US13395608

申请日：2011-10-17

申请人： Wenwu Wang ,  Chao Zhao ,  Kai Han ,  Dapeng Chen

发明人： Wenwu Wang ,  Chao Zhao ,  Kai Han ,  Dapeng Chen

IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/423

CPC分类号： H01L21/82345 ,  H01L21/28114 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

摘要： A semiconductor device and a method for manufacturing the same, the method comprising: providing a semiconductor substrate; forming a dummy gate area on the substrate, forming spacers on sidewalls of the gate area, and forming source and drain areas in the semiconductor substrate on both sides of the dummy gate area, the dummy gate area comprising an interface layer and a dummy gate electrode; forming a dielectric cap layer on the dummy gate area and source and drain areas; planarizing the device with the dielectric cap layer on the source and drain areas as a stop layer; further removing the dummy gate electrode to expose the interface layer; and forming replacement gate area on the interface layer. The thickness of the gate groove may be controlled by the thickness of the dielectric cap layer, and the replacement gates of desired thickness and width may be further formed upon requirements. Thus, the aspect ratio of the gate groove is reduced and a sufficient low gate resistance is ensured.

摘要翻译： 一种半导体器件及其制造方法，所述方法包括：提供半导体衬底; 在所述基板上形成虚拟栅极区域，在所述栅极区域的侧壁上形成间隔物，以及在所述伪栅极区域的两侧形成所述半导体基板中的源极和漏极区域，所述伪栅极区域包括界面层和虚拟栅极电极 ; 在虚拟栅极区域和源极和漏极区域上形成电介质盖层; 使源极和漏极区域上的电介质盖层平坦化作为停止层; 进一步去除虚拟栅电极以露出界面层; 并在界面层上形成替换栅区。 栅极沟槽的厚度可以通过电介质盖层的厚度来控制，并且可以根据需要进一步形成所需厚度和宽度的替换栅极。 因此，栅极沟槽的纵横比减小，并且确保了足够的低栅极电阻。

公开(公告)号：US20130092986A1

公开(公告)日：2013-04-18

申请号：US13395608

申请日：2011-10-17

申请人： Wenwu Wang ,  Chao Zhao ,  Kai Han ,  Dapeng Chen

发明人： Wenwu Wang ,  Chao Zhao ,  Kai Han ,  Dapeng Chen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/82345 ,  H01L21/28114 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

摘要： A semiconductor device and a method for manufacturing the same, the method comprising: providing a semiconductor substrate; forming a dummy gate area on the substrate, forming spacers on sidewalls of the gate area, and forming source and drain areas in the semiconductor substrate on both sides of the dummy gate area, the dummy gate area comprising an interface layer and a dummy gate electrode; forming a dielectric cap layer on the dummy gate area and source and drain areas; planarizing the device with the dielectric cap layer on the source and drain areas as a stop layer; further removing the dummy gate electrode to expose the interface layer; and forming replacement gate area on the interface layer. The thickness of the gate groove may be controlled by the thickness of the dielectric cap layer, and the replacement gates of desired thickness and width may be further formed upon requirements. Thus, the aspect ratio of the gate groove is reduced and a sufficient low gate resistance is ensured.

摘要翻译： 一种半导体器件及其制造方法，所述方法包括：提供半导体衬底; 在所述基板上形成虚拟栅极区域，在所述栅极区域的侧壁上形成间隔物，以及在所述伪栅极区域的两侧形成所述半导体基板中的源极和漏极区域，所述伪栅极区域包括界面层和虚拟栅极电极 ; 在虚拟栅极区域和源极和漏极区域上形成电介质盖层; 使源极和漏极区域上的电介质盖层平坦化作为停止层; 进一步去除虚拟栅电极以露出界面层; 并在界面层上形成替换栅区。 栅极沟槽的厚度可以通过电介质盖层的厚度来控制，并且可以根据需要进一步形成所需厚度和宽度的替换栅极。 因此，栅极沟槽的纵横比减小，并且确保了足够的低栅极电阻。

公开(公告)号：US20120261803A1

公开(公告)日：2012-10-18

申请号：US13394935

申请日：2011-10-17

申请人： Wenwu Wang ,  Chao Zhao ,  Kai Han ,  Dapeng Chen

发明人： Wenwu Wang ,  Chao Zhao ,  Kai Han ,  Dapeng Chen

IPC分类号： H01L21/31 ,  H01L29/02

CPC分类号： C23C14/08 ,  C23C14/5806 ,  C23C16/401 ,  C23C16/56

摘要： The present invention forms Hf1-xSixOy having a cubic phase or a tetragonal phase by doping a specific amount of SiO2 component into the high-K gate dielectric material HfO2 in combination with an optimized thermal processing technique, to thereby acquire a high-K gate dielectric thin film material having a greater bandgap, a higher K value and high thermal stability. Besides, the high-K gate dielectric thin film and a preparation method thereof proposed in the present invention are helpful to solve the problem of crystallization of ultra-thin films.

摘要翻译： 本发明通过与优化的热处理技术结合，将特定量的SiO 2成分掺入到高K栅介质材料HfO 2中，形成具有立方相或四方相的Hf1-xSixOy，从而获得高K栅极电介质 具有较大带隙，较高K值和高热稳定性的薄膜材料。 此外，本发明中提出的高K栅介质薄膜及其制备方法有助于解决超薄膜结晶的问题。

公开(公告)号：US08563415B2

公开(公告)日：2013-10-22

申请号：US13061879

申请日：2010-06-24

申请人： Wenwu Wang ,  Shijie Chen ,  Xiaolei Wang ,  Kai Han ,  Dapeng Chen

发明人： Wenwu Wang ,  Shijie Chen ,  Xiaolei Wang ,  Kai Han ,  Dapeng Chen

IPC分类号： H01L21/3205 ,  H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/28176 ,  H01L29/4916 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/517

摘要： The present invention relates to a method of manufacturing a semiconductor device. After depositing the metal gate electrode material, a layer of oxygen molecule catalyzing layer having a catalyzing function to the oxygen molecules is deposited, and afterwards, a low-temperature PMA annealing process is used to decompose the oxygen molecules in the annealing atmosphere into more active oxygen atoms. These oxygen atoms are diffused into the high-k gate dielectric film through the metal gate to supplement the oxygen vacancies in the high-k film, in order to alleviate oxygen vacancies in the high-k film and improve the quality of the high-k film. According to the present invention, the oxygen vacancies and defects of high-k gate dielectric film will be alleviated, and further, growth of SiOx interface layer having a low dielectric constant caused by the traditional PDA high temperature process may be prevented. Thereby, the EOT of the entire gate dielectric layer may be effectively controlled, and the MOS device may be continuously scaled. Meanwhile, the present invention further provides a semiconductor device obtained according to the above-mentioned method.

摘要翻译： 本发明涉及半导体器件的制造方法。 沉积金属栅电极材料后，沉积具有对氧分子具有催化功能的氧分子催化层，然后使用低温PMA退火工艺将退火气氛中的氧分子分解为更有活性的 氧原子。 这些氧原子通过金属栅极扩散到高k栅极电介质膜中，以补充高k膜中的氧空位，以便减轻高k膜中的氧空位并提高高k的质量 电影。 根据本发明，可以减轻高k栅极电介质膜的氧空位和缺陷，并且可以防止由传统的PDA高温过程引起的具有低介电常数的SiO x界面层的生长。 由此，可以有效地控制整个栅介质层的EOT，并且可以连续地缩放MOS器件。 同时，本发明还提供了根据上述方法获得的半导体器件。

公开(公告)号：US08633098B2

公开(公告)日：2014-01-21

申请号：US13061774

申请日：2010-09-28

申请人： Kai Han ,  Wenwu Wang ,  Xiaolei Wang ,  Shijie Chen ,  Dapeng Chen

发明人： Kai Han ,  Wenwu Wang ,  Xiaolei Wang ,  Shijie Chen ,  Dapeng Chen

IPC分类号： H01L21/28

CPC分类号： H01L29/4908 ,  H01L21/28176 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： The present invention relates to the field of semiconductor manufacturing. The present invention provides a method of manufacturing a semiconductor device, which comprises: providing a semiconductor substrate; forming an interface layer, a gate dielectric layer and a gate electrode on the substrate; forming a metal oxygen absorption layer on the gate electrode; performing a thermal annealing process on the semiconductor device so that the metal oxygen absorption layer absorbs oxygen in the interface layer and the thickness of the interface layer is reduced. By means of the present invention, the thickness of the interface layer can be reduced on one hand, and on the other hand the metal in the metal oxygen absorption layer is made to diffuse into the gate electrode and/or the gate dielectric layer through the annealing process, which further achieves the effects of adjusting the effective work function and controlling the threshold voltage.

摘要翻译： 本发明涉及半导体制造领域。 本发明提供一种制造半导体器件的方法，其包括：提供半导体衬底; 在基板上形成界面层，栅极电介质层和栅电极; 在栅电极上形成金属氧吸收层; 对半导体器件进行热退火处理，使得金属氧吸收层吸收界面层中的氧，并且界面层的厚度减小。 通过本发明，一方面可以减小界面层的厚度，另一方面，通过金属氧化物吸收层中的金属氧化物吸收层中的金属扩散到栅电极和/或栅电介质层 退火工艺，进一步实现了调节有效功函数和控制阈值电压的效果。

公开(公告)号：US20120021596A1

公开(公告)日：2012-01-26

申请号：US13061774

申请日：2010-09-28

申请人： Kai Han ,  Wenwu Wang ,  Xiaolei Wang ,  Shijie Chen ,  Dapeng Chen

发明人： Kai Han ,  Wenwu Wang ,  Xiaolei Wang ,  Shijie Chen ,  Dapeng Chen

IPC分类号： H01L21/28

CPC分类号： H01L29/4908 ,  H01L21/28176 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： The present invention relates to the field of semiconductor manufacturing. The present invention provides a method of manufacturing a semiconductor device, which comprises: providing a semiconductor substrate; forming an interface layer, a gate dielectric layer and a gate electrode on the substrate; forming a metal oxygen absorption layer on the gate electrode; performing a thermal annealing process on the semiconductor device so that the metal oxygen absorption layer absorbs oxygen in the interface layer and the thickness of the interface layer is reduced. By means of the present invention, the thickness of the interface layer can be reduced on one hand, and on the other hand the metal in the metal oxygen absorption layer is made to diffuse into the gate electrode and/or the gate dielectric layer through the annealing process, which further achieves the effects of adjusting the effective work function and controlling the threshold voltage.

摘要翻译： 本发明涉及半导体制造领域。 本发明提供一种制造半导体器件的方法，其包括：提供半导体衬底; 在基板上形成界面层，栅极电介质层和栅电极; 在栅电极上形成金属氧吸收层; 对半导体器件进行热退火处理，使得金属氧吸收层吸收界面层中的氧，并且界面层的厚度减小。 通过本发明，一方面可以减小界面层的厚度，另一方面，通过金属氧化物吸收层中的金属氧化物吸收层中的金属扩散到栅电极和/或栅电介质层 退火工艺，进一步实现了调节有效功函数和控制阈值电压的效果。

公开(公告)号：US20110260255A1

公开(公告)日：2011-10-27

申请号：US13061879

申请日：2010-06-24

申请人： Wenwu Wang ,  Shijie Chen ,  Xiaolei Wang ,  Kai Han ,  Dapeng Chen

发明人： Wenwu Wang ,  Shijie Chen ,  Xiaolei Wang ,  Kai Han ,  Dapeng Chen

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L21/823857 ,  H01L21/28176 ,  H01L29/4916 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/517

摘要： The present invention relates to a method of manufacturing a semiconductor device. After depositing the metal gate electrode material, a layer of oxygen molecule catalyzing layer having a catalyzing function to the oxygen molecules is deposited, and afterwards, a low-temperature PMA annealing process is used to decompose the oxygen molecules in the annealing atmosphere into more active oxygen atoms. These oxygen atoms are diffused into the high-k gate dielectric film through the metal gate to supplement the oxygen vacancies in the high-k film, in order to alleviate oxygen vacancies in the high-k film and improve the quality of the high-k film. According to the present invention, the oxygen vacancies and defects of high-k gate dielectric film will be alleviated, and further, growth of SiOx interface layer having a low dielectric constant caused by the traditional PDA high temperature process may be prevented. Thereby, the EOT of the entire gate dielectric layer may be effectively controlled, and the MOS device may be continuously scaled. Meanwhile, the present invention further provides a semiconductor device obtained according to the above-mentioned method.

摘要翻译： 本发明涉及半导体器件的制造方法。 沉积金属栅电极材料后，沉积具有对氧分子具有催化功能的氧分子催化层，然后使用低温PMA退火工艺将退火气氛中的氧分子分解为更有活性的 氧原子。 这些氧原子通过金属栅极扩散到高k栅极电介质膜中，以补充高k膜中的氧空位，以便减轻高k膜中的氧空位并提高高k的质量 电影。 根据本发明，可以减轻高k栅极电介质膜的氧空位和缺陷，并且可以防止由传统的PDA高温过程引起的具有低介电常数的SiO x界面层的生长。 由此，可以有效地控制整个栅介质层的EOT，并且可以连续地缩放MOS器件。 同时，本发明还提供了根据上述方法获得的半导体器件。

公开(公告)号：US08507991B2

公开(公告)日：2013-08-13

申请号：US13517893

申请日：2012-06-14

申请人： Wenwu Wang ,  Kai Han ,  Shijie Chen ,  Xiaolei Wang ,  Dapeng Chen

发明人： Wenwu Wang ,  Kai Han ,  Shijie Chen ,  Xiaolei Wang ,  Dapeng Chen

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L27/108 ,  H01L31/119 ,  H01L31/062

CPC分类号： H01L21/823857 ,  H01L29/66545 ,  Y10S438/926

摘要： A semiconductor device is provided. A multi-component high-k interface layer containing elements of the substrate is formed from an ultra-thin high-k dielectric material in a single-layer structure of atoms by rapid annealing in the manufacturing of a CMOS transistor by the replacement gate process, and a high-k gate dielectric layer with a higher dielectric constant and a metal gate layer are formed thereon. The EOT of the device is effectively decreased, and the diffusion of atoms in the high-k gate dielectric layer from an upper level thereof is effectively prevented by the optimized high-k interface layer at high-temperature treatment.

摘要翻译： 提供半导体器件。 通过在通过替换栅极工艺制造CMOS晶体管中的快速退火，通过单原子结构的超薄高k电介质材料形成包含衬底元件的多组分高k界面层， 并且在其上形成具有较高介电常数的高k栅极电介质层和金属栅极层。 有效地减少器件的EOT，并且通过在高温处理下的优化的高k界面层有效地防止了高k栅介质层中的原子从其上层的扩散。

公开(公告)号：US20120261761A1

公开(公告)日：2012-10-18

申请号：US13517893

申请日：2012-06-14

申请人： Wenwu Wang ,  Kai Han ,  Shijie Chen ,  Xiaolei Wang ,  Dapeng Chen

发明人： Wenwu Wang ,  Kai Han ,  Shijie Chen ,  Xiaolei Wang ,  Dapeng Chen

IPC分类号： H01L27/088

CPC分类号： H01L21/823857 ,  H01L29/66545 ,  Y10S438/926

摘要： A semiconductor device is provided. A multi-component high-k interface layer containing elements of the substrate is formed from an ultra-thin high-k dielectric material in a single-layer structure of atoms by rapid annealing in the manufacturing of a CMOS transistor by the replacement gate process, and a high-k gate dielectric layer with a higher dielectric constant and a metal gate layer are formed thereon. The EOT of the device is effectively decreased, and the diffusion of atoms in the high-k gate dielectric layer from an upper level thereof is effectively prevented by the optimized high-k interface layer at high-temperature treatment.

摘要翻译： 提供半导体器件。 通过在通过替换栅极工艺制造CMOS晶体管中的快速退火，通过单原子结构的超薄高k电介质材料形成包含衬底元件的多组分高k界面层， 并且在其上形成具有较高介电常数的高k栅极电介质层和金属栅极层。 有效地减少器件的EOT，并且通过在高温处理下的优化的高k界面层有效地防止了高k栅介质层中的原子从其上层的扩散。

公开(公告)号：US08222099B2

公开(公告)日：2012-07-17

申请号：US13063564

申请日：2010-06-24

申请人： Wenwu Wang ,  Kai Han ,  Shijie Chen ,  Xiaolei Wang ,  Dapeng Chen

发明人： Wenwu Wang ,  Kai Han ,  Shijie Chen ,  Xiaolei Wang ,  Dapeng Chen

IPC分类号： H01L27/088

CPC分类号： H01L21/823857 ,  H01L29/66545 ,  Y10S438/926

摘要： A semiconductor device and a method of manufacturing the same are provided. A multi-component high-k interface layer containing elements of the substrate is formed from a ultra-thin high-k dielectric material in a single-layer structure of atoms by rapid annealing in the manufacturing of a CMOS transistor by the replacement gate process, and a high-k gate dielectric layer with a higher dielectric constant and a metal gate layer are formed thereon. The EOT of the device is effectively decreased, and the diffusion of atoms in the high-k gate dielectric layer from an upper level thereof is effectively prevented by the optimized high-k interface layer at high-temperature treatment. Thus, the present invention may also avoid the growth of the interface layers and the degradation of carrier mobility. Furthermore, the present invention may further alleviate the problem of high interface state and interface roughness caused by direct contact of the high-k gate dielectric layer with high dielectric constant and the substrate, and thus the overall performance of the device is effectively enhanced.

摘要翻译： 提供半导体器件及其制造方法。 通过在通过替换栅极工艺制造CMOS晶体管中的快速退火，通过单层原子结构的超薄高k介电材料形成包含衬底元件的多组分高k界面层， 并且在其上形成具有较高介电常数的高k栅极电介质层和金属栅极层。 有效地减少器件的EOT，并且通过在高温处理下的优化的高k界面层有效地防止了高k栅介质层中的原子从其上层的扩散。 因此，本发明还可以避免界面层的生长和载流子迁移率的劣化。 此外，本发明还可以进一步减轻高介电常数和高介电常数直接接触引起的高界面态和界面粗糙度问题，从而有效提高器件的整体性能。