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21.发明申请公开(公告)号：US20200153446A1
公开(公告)日：2020-05-14
申请号：US16594587
申请日：2019-10-07
Applicant: DENSO CORPORATION
Inventor： Kunihiko NAKAMURA , Tomohiro NEZUKA
Abstract: A ΔΣ modulator includes an input circuit having a sampling capacitor, an integration circuit, a quantizer and a D/A converter having a DAC capacitor. The input circuit takes in an analog input voltage in the sampling capacitor in a sampling period, and transfers a charge to the integration circuit in a holding period. The D/A converter takes in an analog potential, to which selection switches are connected in the sampling period based on a digital output of the quantizer, in the DAC capacitor, and subtracts a charge from the integration circuit in the holding period. At this time, since the input circuit and the D/A converter are set so that the holding periods do not overlap with each other, an error caused by the lowering of a feedback factor is suppressed.
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公开(公告)号：US20200112318A1
公开(公告)日：2020-04-09
申请号：US16555042
申请日：2019-08-29
Applicant: DENSO CORPORATION
Inventor： Kunihiko NAKAMURA , Tomohiro NEZUKA
Abstract: A D/A conversion circuit includes: an output terminal connected to an operational amplifier connected to a quantization circuit; a DAC capacitor; a selection switch switching among reference, first and second voltages to apply to the DAC capacitor as an analog potential; a ground switch connecting the DAC capacitor to a ground; and an output switch connecting the DAC capacitor to the output terminal. In a first period, the selection switch selects one of the reference, first and second voltages according to a quantization result value from the quantization circuit, and connects the one to the DAC capacitor, and the ground switch turns on to charge the DAC capacitor. In a second period, the selection switch selects another one of the first and second voltages, and connects the another one to the DAC capacitor, and the output switch turns on to output the analog potential to the output terminal.
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公开(公告)号：US20160373107A1
公开(公告)日：2016-12-22
申请号：US15078013
申请日：2016-03-23
Applicant: DENSO CORPORATION
Inventor： Shogo KAWAHARA , Tomohiro NEZUKA
IPC: H03K17/693
CPC classification number: H03K17/693 , H03M1/00 , H03M3/464
Abstract: First and second p-type transistors are connected in series between an output terminal and a positive power terminal. First and second n-type transistors are connected in series between a node and a negative power terminal. A third p-type transistor is connected between a node and the positive power terminal. Third and fourth n-type transistors are connected in series between the output terminal and a low potential terminal. Fourth and fifth p-type transistors are connected in series between a node and the negative power terminal. A fifth n-type transistor is connected between a node and the negative power terminal. A high potential is outputted without leak current when the first to fifth p-type transistors are turned on and the first to fifth n-type transistors are turned off.
Abstract translation: 第一和第二p型晶体管串联连接在输出端子和正电源端子之间。 第一和第二n型晶体管串联在节点和负电源端子之间。 第三个p型晶体管连接在节点和正电源端子之间。 第三和第四n型晶体管串联在输出端子和低电位端子之间。 第四和第五p型晶体管串联连接在节点和负电源端子之间。 第五个n型晶体管连接在节点和负电源端子之间。 当第一至第五p型晶体管导通并且第一至第五n型晶体管截止时，无泄漏电流输出高电位。
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公开(公告)号：US20250111680A1
公开(公告)日：2025-04-03
申请号：US18889907
申请日：2024-09-19
Inventor： Nobuaki MATSUDAIRA , Tomohiro NEZUKA
Abstract: An estimation device includes a coordinate calculation unit, a feature obtaining unit, and a bird's-eye view generation unit. The coordinate calculation unit calculates three-dimensional coordinates of an object present around a vehicle based on two-dimensional images representing outside of a vehicle captured by a plurality of cameras mounted on the vehicle, by using a self-position estimation method including a visual odometry which calculates the three-dimensional coordinates of the object in sequential two-dimensional images captured by a same camera. The feature obtaining unit obtains a bird's-eye view (BEV) feature, which is a feature in a BEV space, based on the three-dimensional coordinates and at least one of the two-dimensional images by using a BEV estimation algorithm. The bird's-eye view generation unit generates a bird's-eye view based on the BEV feature.
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公开(公告)号：US20240061019A1
公开(公告)日：2024-02-22
申请号：US18448668
申请日：2023-08-11
Inventor： Shotaro WADA , Yoshikazu FURUTA , Tomohiro NEZUKA
IPC: G01R15/14
CPC classification number: G01R15/146
Abstract: A current sensor includes a current detection unit, a relay, a relay control unit, and a resistance value correction circuit. The current detection unit detects a detection target current based on a terminal voltage of a shunt resistor located in series with a path through which the detection target current flows and a detection resistance value for current detection corresponding to a resistance value of the shunt resistor. The relay is located in series with the path through which the detection target current flows. The relay control unit controls the relay to be turned on or off. The resistance value correction circuit calculates the resistance value of the shunt resistor as a calculated resistance value and corrects the detection resistance value based on the calculated resistance value.
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Patent Agency Ranking
公开(公告)号：US20230421170A1
公开(公告)日：2023-12-28
申请号：US18340070
申请日：2023-06-23
Inventor： Shotaro WADA , Tomohiro NEZUKA , Yoshikazu FURUTA
IPC: H03M3/00
Abstract: A delta-sigma modulator includes a capacitively-coupled amplifier, a first integrator, a second integrator, a quantizer, a first switch, a second switch, and a control circuit. The first switch is connected between an input of the capacitively-coupled amplifier and a sampling capacitor of the capacitively-coupled amplifier to execute a chopping operation. The second switch is connected between an output of the capacitively-coupled amplifier and an input of the first integrator to execute a chopping operation. The control circuit executes modulation through the first switch at the input of the capacitively-coupled amplifier, executes demodulation through the second switch at the output of the capacitively-coupled amplifier, and imports an output signal of the capacitively-coupled amplifier into the first integrator after the demodulation.
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公开(公告)号：US20220094309A1
公开(公告)日：2022-03-24
申请号：US17545035
申请日：2021-12-08
Applicant: DENSO CORPORATION
Inventor： Takasuke ITOU , Tomohiro NEZUKA , Yasuaki AOKI , Yuuta NAKAMURA , Takashi YOSHIYA
Abstract: A signal detection circuit includes: a first capacitor having a first terminal connected with a first main terminal of a switching element; a second capacitor having a first terminal connected with a second main terminal of the switching element; and a detection circuit having a differential circuit configuration. The detection circuit receives, as input signals, a signal from a second terminal of the first capacitor and a signal from a second terminal of the second capacitor, detects detection target signals based on the input signals. The detection target signals include a signal of the first main terminal of the switching element and a signal of the second main terminal of the switching element.
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公开(公告)号：US20210075438A1
公开(公告)日：2021-03-11
申请号：US16937804
申请日：2020-07-24
Applicant: DENSO CORPORATION
Inventor： Kunihiko NAKAMURA , Tomohiro NEZUKA , Kazutaka HONDA
Abstract: An A/D conversion device, which operates in one mode including at least one of a ΔΣ mode, a cyclic mode, and a hybrid mode, includes: a first block that processes an analog input signal by a first amplifier; a second block including a second amplifier; a quantization unit that quantizes one of outputs of the first and second blocks; and a control circuit that switches the mode to perform a control corresponding to the mode.
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公开(公告)号：US20190089369A1
公开(公告)日：2019-03-21
申请号：US16196273
申请日：2018-11-20
Applicant: DENSO CORPORATION
Inventor： Tomohiro NEZUKA
Abstract: An A/D converter includes: an integrator circuit executing ΔΣ modulation to an analog signal to be converted; an adder outputting an addition result of at least an output signal of the integrator circuit and a first reference signal as a reference signal of ΔΣ modulation; a quantizer receives an output signal of the integrator circuit, an output signal of the adder, and a second reference signal as a reference signal in cyclic A/D conversion to generate a result of quantization of the output signal of the integrator circuit and the output signal of the adder; and a controller is configured to switch between a ΔΣ modulation mode and a cyclic mode.
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公开(公告)号：US20180212616A1
公开(公告)日：2018-07-26
申请号：US15739206
申请日：2016-07-14
Applicant: DENSO CORPORATION
Inventor： Tomohiro NEZUKA
CPC classification number: H03M1/1245 , H03M1/466 , H03M1/52 , H03M1/54 , H03M3/454
Abstract: An A/D converter is provided with: an integrator that includes an operational amplifier provided with a first input terminal and an output terminal, and an integration capacitor; a quantizer that outputs a quantization result obtained by quantizing an output signal from the operational amplifier; and a DAC that is connected to the first input terminal and determines DAC voltage. The integrator has a feedback switch between the integration capacitor and the output terminal of the operational amplifier. An analog signal as an input signal is inputted between the integration capacitor and the feedback switch. The integration capacitor samples the analog signal. The quantizer performs the quantization based on the output of the operational amplifier. The DAC sequentially subtracts electric charge accumulated in the integration capacitor to thereby change the analog signal to a digital value.
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