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    276-Pin buffered memory module with enhanced fault tolerance and a performance-optimized pin assignment
    22.
    发明授权
    276-Pin buffered memory module with enhanced fault tolerance and a performance-optimized pin assignment 失效
    276引脚缓冲存储器模块，具有增强的容错能力和性能优化的引脚分配

    公开(公告)号：US07529112B2

    公开(公告)日：2009-05-05

    申请号：US11695679

    申请日：2007-04-03

    申请人： Daniel M. Dreps ,  Frank D. Ferraiolo ,  Kevin C. Gower ,  Roger A. Rippens

    发明人： Daniel M. Dreps ,  Frank D. Ferraiolo ,  Kevin C. Gower ,  Roger A. Rippens

    IPC分类号： G11C5/02 ,  G11C5/06

    CPC分类号： G11C5/04

    摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon including a plurality of high-speed bus interface pills arranged on said card for communicating with a plurality of high-speed busses. The high-speed bus interface pins associated with a single high-speed bus are located on one side of the card with respect to a midpoint of the length of the card, thus the pin assignments are defined such that the performance of the DIMM in a system is optimized for high frequency operation.

    摘要翻译： 双列直插式存储器模块（DIMM）包括具有大约151.2至大约151.5毫米的长度的卡，连接到卡的多个单独的本地存储器件以及连接到卡的缓冲器装置，缓冲器装置被配置为将 打包内存界面。 该卡包括至少276个引脚，其构造为包括布置在所述卡上的多个高速总线接口卡，用于与多个高速总线通信。 与单个高速总线相关联的高速总线接口引脚相对于卡的长度的中点位于卡的一侧，因此引脚分配被定义为使得DIMM的性能在 系统针对高频操作进行了优化。

    Data receiver with a programmable reference voltage to optimize timing jitter
    24.
    发明授权
    Data receiver with a programmable reference voltage to optimize timing jitter 失效
    具有可编程参考电压的数据接收器，以优化定时抖动

    公开(公告)号：US07230449B2

    公开(公告)日：2007-06-12

    申请号：US11055805

    申请日：2005-02-11

    申请人： Daniel M. Dreps ,  Frank D. Ferraiolo ,  Robert J. Reese ,  Glen A. Wiedemeier

    发明人： Daniel M. Dreps ,  Frank D. Ferraiolo ,  Robert J. Reese ,  Glen A. Wiedemeier

    IPC分类号： H03K17/16 ,  H04B3/00 ,  H04L25/00

    CPC分类号： H04L25/0292 ,  G06F13/4072 ,  H04L7/0033 ,  H04L25/0272

    摘要： Pseudo-differential drivers and receivers are used to communicate data signals between two or more IC chips. The data paths are aligned using programmable delay circuitry to de-skew each data path. A programmable reference generator is used to generate a reference voltage used by one or a group of receivers to detect the data signals. The reference voltage is adjustable using coarse as well as fine digitally controlled voltage increments. Test signals are sent from the driver to the receiver and the reference voltage is varied over its adjustable range using the coarse and fine adjustment controls while circuitry determines a measure of the detection timing jitter on successive transitions of the test signal. The operational value of the reference voltage is set to the value where the detection timing jitter is determined to be a minimum.

    摘要翻译： 伪差分驱动器和接收器用于在两个或更多个IC芯片之间传送数据信号。 使用可编程延迟电路对数据路径进行对齐，以使每个数据路径发生偏移。 可编程参考发生器用于产生一个或一组接收机使用的参考电压，以检测数据信号。 参考电压可以使用粗调以及精细的数字控制电压增量进行调节。 测试信号从驱动器发送到接收器，并且参考电压在其可调节范围内使用粗略和精细调节控制来改变，而电路确定测试信号的连续转换时的检测定时抖动的量度。 将参考电压的操作值设定为检测定时抖动确定为最小的值。

    Digital phase detector with zero phase offset
    25.
    发明授权
    Digital phase detector with zero phase offset 失效

    公开(公告)号：US08718216B2

    公开(公告)日：2014-05-06

    申请号：US13242053

    申请日：2011-09-23

    申请人： Daniel M. Dreps ,  Kyu-hyoun Kim ,  Glen A. Wiedemeier

    发明人： Daniel M. Dreps ,  Kyu-hyoun Kim ,  Glen A. Wiedemeier

    IPC分类号： H03D3/24

    CPC分类号： H04L7/0037 ,  H03L7/0814 ,  H03L7/085 ,  H03L7/089

    摘要： An embodiment of the invention comprises a digital phase detector with substantially zero phase offset. The digital phase detector receives a clock signal and a reference clock signal and provides a phase indicator signal to identify whether the clock signal leads or lags the reference clock signal. An embodiment of the invention comprises a method that adds substantially zero phase offset in processing an input clock signal and a delayed clock signal to generate a control signal. The control signal is processed in a variable delay line to generate the delayed clock signal. In an embodiment, a first processor comprises a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector receiving a clock signal and generating one or more delayed clock signals, a control signal, and a gated data signal.

    Controllable voltage reference driver for a memory system
    27.
    发明授权
    Controllable voltage reference driver for a memory system 失效
    用于存储系统的可控参考电压驱动器

    公开(公告)号：US08089813B2

    公开(公告)日：2012-01-03

    申请号：US12175555

    申请日：2008-07-18

    申请人： Daniel M. Dreps

    发明人： Daniel M. Dreps

    IPC分类号： G11C16/06

    CPC分类号： G11C29/02 ,  G11C5/04 ,  G11C5/063 ,  G11C5/147 ,  G11C8/08 ,  G11C29/021 ,  G11C29/028

    摘要： A voltage reference driver includes a voltage divider circuit with a voltage reference output node to output a voltage between a first voltage and a second voltage. The voltage reference driver also includes a first selectable impedance circuit coupled to a node at the first voltage and further coupled to the voltage reference output node, and a second selectable impedance circuit coupled to a node at the second voltage and further coupled to the voltage reference output node. Combinations of the first selectable impedance circuit and the second selectable impedance circuit are selectable such that a constant impedance is maintained at the voltage reference output node within a threshold value.

    摘要翻译： 电压参考驱动器包括具有电压参考输出节点的分压器电路，以输出第一电压和第二电压之间的电压。 电压参考驱动器还包括耦合到处于第一电压的节点的第一可选择阻抗电路并进一步耦合到电压参考输出节点，以及第二可选阻抗电路，耦合到处于第二电压的节点，并且还耦合到电压基准 输出节点。 可选择第一可选择阻抗电路和第二可选择阻抗电路的组合，使得在阈值内的电压参考输出节点处保持恒定的阻抗。

    Multimodal memory controllers
    30.
    发明授权
    Multimodal memory controllers 失效
    多模式内存控制器

    公开(公告)号：US07773689B2

    公开(公告)日：2010-08-10

    申请号：US11670491

    申请日：2007-02-02

    申请人： Daniel M. Dreps ,  Dhaval R. Sejpal ,  Glen A. Wiedemeier

    发明人： Daniel M. Dreps ,  Dhaval R. Sejpal ,  Glen A. Wiedemeier

    IPC分类号： H04B3/00

    CPC分类号： G06F13/1694

    摘要： Multimodal memory controllers are disclosed that include: a transmitter having a first input signal line, a second input signal line, a first output signal line, a second output signal line, a first single-ended driver, a second single-ended driver, a differential transmitter, and a mode control signal line, the mode control signal line having asserted upon it a mode control signal, the transmitter configured to operate the output signal lines using the single-ended drivers at a first voltage when the mode control signal is a first value and to operate the output signal lines using the differential transmitter at a second voltage when the mode control signal is a second value, and the transmitter configured to protect the differential transmitter from the first voltage when the mode control signal is the first value.

    摘要翻译： 公开了多模式存储器控制器，其包括：具有第一输入信号线，第二输入信号线，第一输出信号线，第二输出信号线，第一单端驱动器，第二单端驱动器， 差分发射器和模式控制信号线，模式控制信号线已经向模式控制信号断言，所述发射机被配置为当模式控制信号为模拟控制信号时以第一电压使用单端驱动器来操作输出信号线 并且当所述模式控制信号是第二值时，使用所述差分发射机在所述第二电压下操作所述输出信号线，并且所述发射机被配置为当所述模式控制信号是所述第一值时保护所述差分发射机不受所述第一电压的影响。