公开(公告)号：US06521510B1

公开(公告)日：2003-02-18

申请号：US10105998

申请日：2002-03-25

申请人： Philip Fisher ,  Darin A. Chan

发明人： Philip Fisher ,  Darin A. Chan

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/76283

摘要： A method of isolation of active islands on a silicon-on-insulator semiconductor device, including steps of (1) providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric insulation layer and a silicon substrate; (2) etching through the silicon active layer to form an isolation trench, the isolation trench defining an active island in the silicon active layer, the active island having at least one upper sharp corner; (3) rounding the at least one upper sharp corner of the active island, whereby at least one strained edge portion of the active island is formed; (4) removing at least a part of the at least one strained edge portion; and (5) at least partially filling the isolation trench with a dielectric trench isolation material to form a shallow trench isolation structure. An SOI wafer semiconductor device having a STI isolation structure free from a strained edge portion and a bird's beak.

摘要翻译： 一种隔离绝缘体上半导体器件上的有源岛的方法，包括以下步骤：（1）提供具有硅有源层，介电绝缘层和硅衬底的绝缘体上硅半导体晶片; （2）蚀刻穿过硅有源层以形成隔离沟槽，隔离沟槽在硅有源层中限定有源岛，活性岛具有至少一个上尖锐角; （3）对活性岛的至少一个上尖锐角进行四舍五入，由此形成活性岛的至少一个应变边缘部分; （4）去除所述至少一个应变边缘部分的至少一部分; 和（5）用绝缘沟槽隔离材料至少部分地填充隔离沟槽以形成浅沟槽隔离结构。 具有没有应变边缘部分和鸟喙的STI隔离结构的SOI晶片半导体器件。

公开(公告)号：US06403492B1

公开(公告)日：2002-06-11

申请号：US09776307

申请日：2001-02-02

申请人： Matthew S. Buynoski ,  Darin A. Chan

发明人： Matthew S. Buynoski ,  Darin A. Chan

IPC分类号： H01L21302

CPC分类号： H01L21/76224 ,  H01L21/31053 ,  H01L21/31055

摘要： A method of trench isolation includes removal of insulation material after planarization of the insulation material and before stripping of a nitride layer such as polish stop layer. The removal of insulation material may be accomplished, for example, by etching. The amount of material removed may be selected so that a surface of the device is substantially planar after one or more subsequent processing steps.

摘要翻译： 沟槽隔离的方法包括在绝缘材料平坦化之后以及剥离诸如抛光停止层之类的氮化物层之前去除绝缘材料。 绝缘材料的去除可以例如通过蚀刻来实现。 可以选择去除的材料的量，使得在一个或多个后续处理步骤之后，该装置的表面基本上是平面的。

公开(公告)号：US07223640B2

公开(公告)日：2007-05-29

申请号：US11071375

申请日：2005-03-03

申请人： Mario M. Pelella ,  Darin A. Chan ,  Simon S. Chan

发明人： Mario M. Pelella ,  Darin A. Chan ,  Simon S. Chan

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/425

CPC分类号： H01L21/823481 ,  H01L21/84 ,  H01L27/1203

摘要： A semiconductor component having analog and logic circuit elements manufactured from an SOI substrate and a method for manufacturing the semiconductor component. An SOI substrate has a support wafer coupled to an active wafer through an insulating material. Openings are formed in the active wafer, extend through the insulating material, and expose portions of the support wafer. Epitaxial semiconductor material is grown on the exposed portions of the support wafer. Analog circuitry is manufactured from the epitaxially grown semiconductor material and high performance logic circuitry is manufactured from the active wafer. The processing steps for manufacturing the analog circuitry are decoupled from the steps for manufacturing the high performance logic circuitry. A substrate contact is made from a portion of the epitaxially grown semiconductor material that is electrically isolated from the portion in which the analog circuitry is manufactured.

摘要翻译： 具有由SOI衬底制造的模拟和逻辑电路元件的半导体元件和用于制造半导体元件的方法。 SOI衬底具有通过绝缘材料耦合到有源晶片的支撑晶片。 开口形成在有源晶片中，延伸穿过绝缘材料，并暴露支撑晶片的部分。 外延半导体材料在支撑晶片的暴露部分上生长。 模拟电路由外延生长的半导体材料制成，高性能逻辑电路由有源晶片制造。 用于制造模拟电路的处理步骤与用于制造高性能逻辑电路的步骤分离。 从与制造模拟电路的部分电隔离的外延生长的半导体材料的一部分制成衬底接触。

公开(公告)号：US06780776B1

公开(公告)日：2004-08-24

申请号：US10023328

申请日：2001-12-20

申请人： Wen-Jie Qi ,  John G. Pellerin ,  William G. En ,  Mark W. Michael ,  Darin A. Chan

发明人： Wen-Jie Qi ,  John G. Pellerin ,  William G. En ,  Mark W. Michael ,  Darin A. Chan

IPC分类号： H01L21302

CPC分类号： H01L29/6659 ,  H01L21/28247 ,  H01L21/31116 ,  H01L21/3185 ,  H01L29/6656

摘要： A method of forming a semiconductor device provides a gate electrode on a substrate and forms a polysilicon reoxidation layer over the substrate and the gate electrode. A nitride layer is deposited over the polysilicon reoxidation layer and anisotropically etched The etching stops on the polysilicon reoxidation layer, with nitride offset spacers being formed on the gate electrode. The use of the polysilicon reoxidation layer as an etch stop layer prevents the gouging of the silicon substrate underneath the nitride layer, while allowing the offset spacers to be formed.

摘要翻译： 形成半导体器件的方法在衬底上提供栅电极，并在衬底和栅电极上形成多晶硅再氧化层。 氮化物层沉积在多晶硅再氧化层上并各向异性蚀刻。多晶硅再氧化层上的蚀刻停止，在栅电极上形成氮化物偏移间隔物。 使用多晶硅再氧化层作为蚀刻停止层防止在氮化物层下方的硅衬底的气蚀，同时允许形成偏移间隔物。

公开(公告)号：US5614446A

公开(公告)日：1997-03-25

申请号：US479873

申请日：1995-06-07

申请人： Seshadri Ramaswami ,  Darin A. Chan

发明人： Seshadri Ramaswami ,  Darin A. Chan

IPC分类号： C23C14/50 ,  H01L21/687 ,  H01L21/28

CPC分类号： H01L21/68721 ,  C23C14/50 ,  H01L21/6875 ,  H01L2223/54493

摘要： A holding apparatus, a metal deposition system and a wafer processing method which preserve topographical marks, including those used as alignment targets, on a semiconductor wafer by preventing metal from depositing on such marks during metal deposition. The invention eliminates the need to use window mask and etch techniques to provide replication of topographical marks on a newly formed metal layer when a CMP planarization technique is used prior to metal deposition. As a result, cost, cycle time and yield loss due to the additional window mask and etch steps can be eliminated. The holding apparatus includes a wafer retainer for retaining a wafer which has at least one topographical mark and a clamp ring with at least one tab. The wafer is pressed against the clamp ring by the retainer for securing the wafer in the retainer. Each tab is positioned directly above a corresponding one of the topographical mark and has an area big enough to cover such mark for avoiding metal being deposited on such mark during metal deposition of the wafer. The metal deposition system comprises a depositing system for depositing a layer of a selected metal onto the wafer. The metal deposition system also includes a holding apparatus constructed in accordance with the present invention for holding the wafer during metal deposition. The processing method comprises forming an optically transparent oxide layer over the wafer which includes at least one topographical mark and providing a metallized layer over the wafer except over such mark.

摘要翻译： 一种保持装置，金属沉积系统和晶片处理方法，其通过在金属沉积期间防止金属沉积在这些标记上，在半导体晶片上保留包括那些用作对准靶的形貌标记。 当在金属沉积之前使用CMP平坦化技术时，本发明消除了使用窗口掩模和蚀刻技术来提供新形成的金属层上的形貌标记的复制的需要。 结果，可以消除由于额外的窗口掩模和蚀刻步骤引起的成本，周期时间和屈服损失。 保持装置包括用于保持具有至少一个形状标记的晶片和具有至少一个突片的夹紧环的晶片保持器。 通过保持器将晶片压靠在夹紧环上，以将晶片固定在保持器中。 每个凸片位于相应的一个地形标记的正上方，并具有足够大的面积以覆盖这种标记，以避免在晶片的金属沉积期间金属沉积在该标记上。 金属沉积系统包括用于将选定金属层沉积到晶片上的沉积系统。 金属沉积系统还包括根据本发明构造的用于在金属沉积期间保持晶片的保持装置。 该处理方法包括在晶片之上形成光学透明的氧化物层，其包括至少一个地形标记，并且在该晶片之外提供金属化层，除了该标记之外。

公开(公告)号：US5456756A

公开(公告)日：1995-10-10

申请号：US300273

申请日：1994-09-02

申请人： Seshadri Ramaswami ,  Darin A. Chan

发明人： Seshadri Ramaswami ,  Darin A. Chan

IPC分类号： C23C14/50 ,  H01L21/687 ,  C23C14/00

CPC分类号： H01L21/68721 ,  C23C14/50 ,  H01L21/6875 ,  H01L2223/54493

摘要： A holding apparatus, a metal deposition system and a wafer processing method which preserve topographical marks, including those used as alignment targets, on a semiconductor wafer by preventing metal from depositing on such marks during metal deposition. The invention eliminates the need to use window mask and etch techniques to provide replication of topographical marks on a newly formed metal layer when a CMP planarization technique is used prior to metal deposition. As a result, cost, cycle time and yield loss due to the additional window mask and etch steps can be eliminated. The holding apparatus includes a wafer retainer for retaining a wafer which has at least one topographical mark and a clamp ring with at least one tab. The wafer is pressed against the clamp ring by the retainer for securing the wafer in the retainer. Each tab is positioned directly above a corresponding one of the topographical mark and has an area big enough to cover such mark for avoiding metal being deposited on such mark during metal deposition of the wafer. The metal deposition system comprises a depositing system for depositing a layer of a selected metal onto the wafer. The metal deposition system also includes a holding apparatus constructed in accordance with the present invention for holding the wafer during metal deposition. The processing method comprises forming an optically transparent oxide layer over the wafer which includes at least one topographical mark and providing a metallized layer over the wafer except over such mark.

摘要翻译： 一种保持装置，金属沉积系统和晶片处理方法，其通过在金属沉积期间防止金属沉积在这些标记上，在半导体晶片上保留包括那些用作对准靶的形貌标记。 当在金属沉积之前使用CMP平坦化技术时，本发明消除了使用窗口掩模和蚀刻技术来提供新形成的金属层上的形貌标记的复制的需要。 结果，可以消除由于额外的窗口掩模和蚀刻步骤引起的成本，周期时间和屈服损失。 保持装置包括用于保持具有至少一个形状标记的晶片和具有至少一个突片的夹紧环的晶片保持器。 通过保持器将晶片压靠在夹紧环上，以将晶片固定在保持器中。 每个凸片位于相应的一个地形标记的正上方，并具有足够大的面积以覆盖这种标记，以避免在晶片的金属沉积期间金属沉积在该标记上。 金属沉积系统包括用于将选定金属层沉积到晶片上的沉积系统。 金属沉积系统还包括根据本发明构造的用于在金属沉积期间保持晶片的保持装置。 该处理方法包括在晶片之上形成光学透明的氧化物层，其包括至少一个地形标记，并且在该晶片之外提供金属化层，除了该标记之外。

公开(公告)号：US07880229B2

公开(公告)日：2011-02-01

申请号：US11874454

申请日：2007-10-18

申请人： Sriram Madhavan ,  Qiang Chen ,  Darin A. Chan ,  Jung-Suk Goo

发明人： Sriram Madhavan ,  Qiang Chen ,  Darin A. Chan ,  Jung-Suk Goo

IPC分类号： H01L27/12

CPC分类号： H01L29/78615 ,  H01L22/34

摘要： A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.

摘要翻译： 提供了一种身体搭接测试结构及其制造方法。 晶体管包括形成在半导体材料层中的主体结合半导体绝缘体（SOI）晶体管，该晶体管包括具有基本恒定的栅极长度L的十字形栅极结构。绝缘阻挡层能够形成间隔区域 所述半导体材料层将所述源极和漏极区域与所述主体连接区域分开。 具有与本征晶体管主体基本上相同的反转特性的导电沟道通过间隔区将主体连接到本征晶体管本体。

公开(公告)号：US20080124884A1

公开(公告)日：2008-05-29

申请号：US11467634

申请日：2006-08-28

申请人： Mario M. Pelella ,  Darin A. Chan

发明人： Mario M. Pelella ,  Darin A. Chan

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L21/823878 ,  H01L27/0629

摘要： Methods are provided for fabricating an SOI component on a semiconductor layer/insulator/substrate structure including a diode region formed in the substrate. The method comprises, in accordance with one embodiment, forming a shallow trench isolation (STI) region extending through the semiconductor layer to the insulator. A layer of polycrystalline silicon is deposited overlying the STI and the semiconductor layer and is patterned to form a polycrystalline silicon mask comprising at least a first mask region and a second mask region. First and second openings are etched through the STI and the insulator using the mask as an etch mask. N— and P-type ions are implanted into the diode region through the openings to form the anode and cathode of the diode. The anode and cathode are closely spaced and precisely aligned to each other by the polycrystalline silicon mask. Electrical contacts are made to the anode and cathode.

摘要翻译： 提供了用于在包括在衬底中形成的二极管区域的半导体层/绝缘体/衬底结构上制造SOI部件的方法。 该方法包括根据一个实施例，形成穿过半导体层延伸到绝缘体的浅沟槽隔离（STI）区域。 沉积覆盖STI和半导体层的多晶硅层，并且被图案化以形成至少包括第一掩模区域和第二掩模区域的多晶硅掩模。 使用掩模作为蚀刻掩模，通过STI和绝缘体蚀刻第一和第二开口。 N型和P型离子通过开口注入二极管区域，形成二极管的阳极和阴极。 阳极和阴极通过多晶硅掩模彼此紧密间隔并精确对准。 电触点被制成阳极和阴极。

公开(公告)号：US07250667B2

公开(公告)日：2007-07-31

申请号：US11306663

申请日：2006-01-05

申请人： Darin A. Chan ,  Simon Siu-Sing Chan ,  Paul L. King

发明人： Darin A. Chan ,  Simon Siu-Sing Chan ,  Paul L. King

IPC分类号： H01L29/00

CPC分类号： H01L27/112 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit is provided with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. Source/drain junctions are in the semiconductor substrate. A silicide is on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is above the semiconductor substrate. Contacts and connection points are in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.

摘要翻译： 集成电路设置有半导体衬底，当半导体衬底反应以形成这种硅化物时，半导体衬底被掺杂为具有与硅化物的顶表面分离的类型的可氧化掺杂剂的设定浓度。 栅极电介质位于半导体衬底上，栅极位于栅极电介质上。 源极/漏极结在半导体衬底中。 硅化物在源极/漏极结上，掺杂剂分离到硅化物的顶表面。 分离的掺杂剂的顶表面上的掺杂剂被氧化以在硅化物之上形成氧化掺杂剂的绝缘层。 层间电介质在半导体衬底之上。 触点和连接点位于硅化物之上的氧化掺杂剂的绝缘层的层间电介质中。

公开(公告)号：US07015076B1

公开(公告)日：2006-03-21

申请号：US10791098

申请日：2004-03-01

申请人： Darin A. Chan ,  Simon Siu-Sing Chan ,  Paul L. King

发明人： Darin A. Chan ,  Simon Siu-Sing Chan ,  Paul L. King

IPC分类号： H01L21/82

CPC分类号： H01L27/112 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided of forming an integrated circuit with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is deposited above the semiconductor substrate. Contacts and connection points are then formed in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.

摘要翻译： 提供了一种形成集成电路的方法，该半导体衬底在半导体衬底反应形成这种硅化物时，掺杂有一定类型的可氧化掺杂剂的分解与硅化物顶表面的浓度。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结上形成硅化物，掺杂剂分离到硅化物的顶表面。 分离的掺杂剂的顶表面上的掺杂剂被氧化以在硅化物之上形成氧化掺杂剂的绝缘层。 在半导体衬底上沉积层间电介质。 接触点和连接点然后在层间电介质中形成到硅化物之上的氧化掺杂剂的绝缘层。