Isolation of input/output adapter traffic class/virtual channel and input/output ordering domains
    21.
    发明授权
    Isolation of input/output adapter traffic class/virtual channel and input/output ordering domains 失效
    输入/输出适配器流量类/虚拟通道和输入/输出排序域的隔离

    公开(公告)号:US07266631B2

    公开(公告)日:2007-09-04

    申请号:US10902611

    申请日:2004-07-29

    CPC分类号: G06F13/126

    摘要: Method, apparatus and system for controlling input/output adapter data flow operations in a data processing system that includes at least one of a traffic class mechanism in conjunction with virtual channel resources so as to be able to associate Load/Store and DMA flows to/from an input/output adapter, and a relaxed ordering mechanism for associating a relaxed ordering bit to Load/Store operations to an input/output adapter. Functionality for controlling the input/output adapter data flow is provided in a host bridge that connects the input/output adapter to a system bus of the data processing system.

    摘要翻译: 用于控制数据处理系统中的输入/输出适配器数据流操作的方法,装置和系统,该数据处理系统包括结合虚拟信道资源的业务类机制中的至少一个,以便能够将加载/存储和DMA流关联到/ 以及用于将放松的排序位与加载/存储操作相关联的输入/输出适配器的放松排序机制。 用于控制输入/输出适配器数据流的功能在将输入/输出适配器连接到数据处理系统的系统总线的主机桥中提供。

    Location-based non-uniform allocation of memory resources in memory mapped input/output fabric
    22.
    发明授权
    Location-based non-uniform allocation of memory resources in memory mapped input/output fabric 失效
    内存映射输入/输出结构中的基于位置的非均匀分配内存资源

    公开(公告)号:US07200687B2

    公开(公告)日:2007-04-03

    申请号:US10671365

    申请日:2003-09-25

    IPC分类号: G06F3/00

    CPC分类号: G06F12/0653 G06F2212/206

    摘要: An apparatus, program product and method in which a memory address space is allocated non-uniformly to IO resources in a memory mapped IO fabric based upon the locations of individual IO endpoints to which such IO resources are coupled. In a PCI-based environment, for example, PCI adapters are allocated memory address ranges in a PCI bus address space based upon the locations of the particular slots within which the PCI adapters are mounted.

    摘要翻译: 一种装置,程序产品和方法,其中基于所述IO资源耦合到的各个IO端点的位置,存储器地址空间被非均匀地分配给存储器映射的IO结构中的IO资源。 例如,在基于PCI的环境中,PCI适配器基于PCI适配器所在的特定时隙的位置,在PCI总线地址空间中分配存储器地址范围。

    Method and system for informing an operating system in a system area network when a new device is connected
    24.
    发明授权
    Method and system for informing an operating system in a system area network when a new device is connected 有权
    连接新设备时通知系统区域网络中的操作系统的方法和系统

    公开(公告)号:US07136907B1

    公开(公告)日:2006-11-14

    申请号:US09692342

    申请日:2000-10-19

    IPC分类号: G06F15/177

    CPC分类号: G06F15/16

    摘要: A method and system are provided for dynamically informing an operating system (OS) of a distributed computer system, when a (new) device is added on the network. An OS registers with the subnet administrator (SA) to be notified when a new component is added to the subnet and placed in a partition to which the OS has access. The subnet manager (SM) initializes and configures the new component that is added and, through the partition manager, associates the component to one or more partitions of the subnet. The SA then notifies the OSs with access to the partition(s) to which the component is associated and that have a right to access the new component that the new component is available to the OS. Following, the OS updates a database of available components to include the new component and establishes communication with the new component.

    摘要翻译: 当在网络上添加(新)设备时,提供了一种用于动态地通知分布式计算机系统的操作系统(OS)的方法和系统。 操作系统向子网管理员(SA)注册,当新组件添加到子网并放置在操作系统可以访问的分区时通知该子网。 子网管理器(SM)初始化并配置添加的新组件,并通过分区管理器将组件与子网的一个或多个分区相关联。 然后,SA通知操作系统对该组件关联的分区的访问,并且有权访问新组件以使新组件可用于OS。 以下,OS更新可用组件的数据库以包括新组件并建立与新组件的通信。

    Method for processing PCI interrupt signals in a logically partitioned guest operating system
    25.
    发明授权
    Method for processing PCI interrupt signals in a logically partitioned guest operating system 有权
    在逻辑分区客户机操作系统中处理PCI中断信号的方法

    公开(公告)号:US06766398B2

    公开(公告)日:2004-07-20

    申请号:US09836687

    申请日:2001-04-17

    IPC分类号: G06F1300

    CPC分类号: G06F13/24 G06F9/45541

    摘要: The present invention generally provides embodiments relative to a method for PCI interrupt routing in a logically partitioned guest operating system. The method, which may be embodied upon a computer readable medium and executed by a processor, may include the steps of locating primary PCI buses, initializing IRQ tables, locating hardware interrupt sources, and activating an interrupt handling process. Embodiments of the present invention include the capability to mask and unmask function interrupts for each device associated with the guest operating system, wherein the process of masking and unmasking function interrupts may include calling a hypervisor to associate an OS IRQ number with a slot.

    摘要翻译: 本发明一般提供了相对于逻辑分区的客户机操作系统中的PCI中断路由方法的实施例。 可以在计算机可读介质上体现并由处理器执行的方法可以包括以下步骤:定位主PCI总线,初始化IRQ表,定位硬件中断源以及激活中断处理过程。 本发明的实施例包括对与客户机操作系统相关联的每个设备进行屏蔽和解除掩蔽功能中断的能力,其中屏蔽和解除功能中断的过程可以包括调用管理程序以将OS IRQ号码与时隙相关联。

    Computer input/output (I/O) interface with dynamic I/O adaptor processor bindings
    29.
    发明授权
    Computer input/output (I/O) interface with dynamic I/O adaptor processor bindings 失效
    具有动态I / O适配器处理器绑定的计算机输入/输出(I / O)接口

    公开(公告)号:US06529978B1

    公开(公告)日:2003-03-04

    申请号:US09511506

    申请日:2000-02-23

    IPC分类号: G06F1300

    CPC分类号: G06F13/124

    摘要: An apparatus, program product and method to dynamically control the bindings between Input/Output Adaptors (IOA's) and Input/Output Processors (IOP's) in a hierarchical I/O interface of a computer, such that an IOA can be dynamically reassigned from one IOP to another IOP such that the latter IOP takes over management of data transfer between the processing complex of the computer and the IOA from the former IOP. At least partial system availability is maintained in the computer during dynamic reassignment to minimize system downtime and simplify maintenance operations on the computer.

    摘要翻译: 一种用于动态地控制计算机的分层I / O接口中的输入/输出适配器(IOA)和输入/输出处理器(IOP)之间的绑定的装置,程序产品和方法,使得IOA可以从一个IOP动态地重新分配 使得后者IOP接管来自前者IOP的计算机的处理复合体和IOA之间的数据传输的管理。 在动态重新分配期间,至少部分系统可用性在计算机中保持最小化,以最大限度地减少系统停机时间并简化计算机上的维护操作。

    Specifying wrap register for storing memory address to store completion status of instruction to external device
    30.
    发明授权
    Specifying wrap register for storing memory address to store completion status of instruction to external device 失效
    指定用于存储存储器地址的包装寄存器,以将指令的完成状态存储到外部设备

    公开(公告)号:US06275876B1

    公开(公告)日:2001-08-14

    申请号:US09316243

    申请日:1999-05-21

    IPC分类号: G06F1312

    CPC分类号: G06F13/126

    摘要: A computing system includes a processing system, at least a first register, and a control system. The processing system generates a first instruction set and a first address for storing a first completion status for the first instruction set. The first register receives the first address from the processing system. The control system communicates the first instruction set received from the processing system to an external device. The control system receives the first completion status from the external device, accesses the first register to determine the first address for the first instruction set, and stores the first completion status in the determined first address.

    摘要翻译: 计算系统包括处理系统,至少第一寄存器和控制系统。 处理系统产生第一指令集和第一地址,用于存储第一指令集的第一完成状态。 第一个寄存器从处理系统接收第一个地址。 控制系统将从处理系统接收的第一指令集传送到外部设备。 控制系统从外部设备接收第一完成状态,访问第一寄存器以确定第一指令集的第一地址,并将第一完成状态存储在所确定的第一地址中。