摘要:
Method, apparatus and system for controlling input/output adapter data flow operations in a data processing system that includes at least one of a traffic class mechanism in conjunction with virtual channel resources so as to be able to associate Load/Store and DMA flows to/from an input/output adapter, and a relaxed ordering mechanism for associating a relaxed ordering bit to Load/Store operations to an input/output adapter. Functionality for controlling the input/output adapter data flow is provided in a host bridge that connects the input/output adapter to a system bus of the data processing system.
摘要:
An apparatus, program product and method in which a memory address space is allocated non-uniformly to IO resources in a memory mapped IO fabric based upon the locations of individual IO endpoints to which such IO resources are coupled. In a PCI-based environment, for example, PCI adapters are allocated memory address ranges in a PCI bus address space based upon the locations of the particular slots within which the PCI adapters are mounted.
摘要:
An apparatus, program product and method dynamically bind Message Signaled Interrupt (MSI) resources shared by a plurality of clients to an interrupt facility in an MSI-capable computer. In addition, management of such bindings may be implemented using a platform independent interrupt manager capable of managing multiple MSI bindings between MSI resources to an interrupt facility, and interfaced with an underlying hardware platform of a computer through platform-specific encapsulation program code.
摘要:
A method and system are provided for dynamically informing an operating system (OS) of a distributed computer system, when a (new) device is added on the network. An OS registers with the subnet administrator (SA) to be notified when a new component is added to the subnet and placed in a partition to which the OS has access. The subnet manager (SM) initializes and configures the new component that is added and, through the partition manager, associates the component to one or more partitions of the subnet. The SA then notifies the OSs with access to the partition(s) to which the component is associated and that have a right to access the new component that the new component is available to the OS. Following, the OS updates a database of available components to include the new component and establishes communication with the new component.
摘要:
The present invention generally provides embodiments relative to a method for PCI interrupt routing in a logically partitioned guest operating system. The method, which may be embodied upon a computer readable medium and executed by a processor, may include the steps of locating primary PCI buses, initializing IRQ tables, locating hardware interrupt sources, and activating an interrupt handling process. Embodiments of the present invention include the capability to mask and unmask function interrupts for each device associated with the guest operating system, wherein the process of masking and unmasking function interrupts may include calling a hypervisor to associate an OS IRQ number with a slot.
摘要:
An I/O system including a processor complex and system main memory connected to I/O adapters via I/O adapters and I/O bus. A message transport mechanism and method stores an upstream message queue and a downstream message queue in system main memory. Queue addresses are stored both in system main memory and designated registers of I/O adapters. The I/O adapters utilize the queue addresses to manage the transfer of downstream command messages and to send upstream response messages to the system main memory via direct memory access across the I/O bus.
摘要:
An apparatus, program product and method dynamically bind Message Signaled Interrupt (MSI) resources shared by a plurality of clients to an interrupt facility in an MSI-capable computer. In addition, management of such bindings may be implemented using a platform independent interrupt manager capable of managing multiple MSI bindings between MSI resources to an interrupt facility, and interfaced with an underlying hardware platform of a computer through platform-specific encapsulation program code.
摘要:
A method, which may be embodied upon a computer readable medium and executed by a processor, for detecting PCI buses in a logically partitioned system. The method may include determining PCI buses that are accessible to a guest operating system via querying a hypervisor, generating a PCI controller list, wherein a PCI controller exists for each determined PCI bus, and constructing a PCI bus structure for each PCI controller in the PCI controller list. The method may further include calling a platform dependent device detection code to detect PCI devices accessible to the logically partitioned system, and connecting to each function of each detected PCI device to authorize the guest operating system to conduct configuration IO operations thereon through a platform dependent code operation.
摘要:
An apparatus, program product and method to dynamically control the bindings between Input/Output Adaptors (IOA's) and Input/Output Processors (IOP's) in a hierarchical I/O interface of a computer, such that an IOA can be dynamically reassigned from one IOP to another IOP such that the latter IOP takes over management of data transfer between the processing complex of the computer and the IOA from the former IOP. At least partial system availability is maintained in the computer during dynamic reassignment to minimize system downtime and simplify maintenance operations on the computer.
摘要:
A computing system includes a processing system, at least a first register, and a control system. The processing system generates a first instruction set and a first address for storing a first completion status for the first instruction set. The first register receives the first address from the processing system. The control system communicates the first instruction set received from the processing system to an external device. The control system receives the first completion status from the external device, accesses the first register to determine the first address for the first instruction set, and stores the first completion status in the determined first address.