公开(公告)号：US20110086470A1

公开(公告)日：2011-04-14

申请号：US12972232

申请日：2010-12-17

申请人： Terry McDaniel ,  James Green ,  Mark Fischer

发明人： Terry McDaniel ,  James Green ,  Mark Fischer

IPC分类号： H01L21/8229

CPC分类号： H01L27/105 ,  H01L21/823475 ,  H01L21/823871 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11531 ,  H01L29/66545

摘要： Memory devices, such as DRAM memory devices, may include one or more metal layers above a local interconnect of the DRAM memory that make contact to lower gate regions of the memory device. As the size of semiconductor components decreases and circuit densities increase, the density of the metal routing in these upper metal layers becomes increasingly difficult to fabricate. By providing additional metal routing in the lower gate regions that may be coupled to the upper metal layers, the spacing requirements of the upper metal layers may be eased, while maintaining the size of the semiconductor device. In addition, the additional metal routing formed in the gate regions of the memory devices may be disposed parallel to other metal contacts in a strapping configuration, thus reducing a resistance of the metal contacts, such as buried digit lines of a DRAM memory cell.

摘要翻译： 诸如DRAM存储器件的存储器件可以包括与存储器件的下部栅极区域接触的DRAM存储器的局部互连上方的一个或多个金属层。 随着半导体元件的尺寸减小和电路密度增加，这些上层金属层中的金属布线的密度越来越难于制造。 通过在可以耦合到上金属层的下栅极区域中提供额外的金属布线，可以在保持半导体器件的尺寸的同时，缓和上金属层的间隔要求。 此外，形成在存储器件的栅极区域中的附加金属布线可以以带状构造平行于其它金属触点设置，从而降低金属触点（例如DRAM存储器单元的掩埋数字线）的电阻。

公开(公告)号：US07880232B2

公开(公告)日：2011-02-01

申请号：US11591627

申请日：2006-11-01

申请人： Mark Fischer ,  T. Earl Allen ,  H. Montgomery Manning

发明人： Mark Fischer ,  T. Earl Allen ,  H. Montgomery Manning

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/7853 ,  Y10S438/947

摘要： A process may include first etching a trench isolation dielectric through a dielectric hard mask that abuts the sidewall of a fin semiconductor. The first etch can be carried out to expose at least a portion of the sidewall, causing the dielectric hard mask to recede to a greater degree in the lateral direction than the vertical direction. The process may include second etching the fin semiconductor to achieve a thinned semiconductor fin, which has receded beneath the shadow of the laterally receded hard mask. The thinned semiconductor fin may have a characteristic dimension that can exceed photolithography limits. Electronic devices may include the thinned semiconductor fin as part of a field effect transistor.

摘要翻译： 工艺可以包括首先通过与散热片半导体的侧壁邻接的电介质硬掩模蚀刻沟槽隔离电介质。 可以执行第一蚀刻以暴露侧壁的至少一部分，使得电介质硬掩模在横向方向上比垂直方向更大程度地退回。 该方法可以包括第二蚀刻鳍式半导体以实现减薄的半导体鳍片，其已经在横向后退的硬掩模的阴影之下后退。 减薄的半导体鳍片可以具有可超过光刻极限的特征尺寸。 电子器件可以包括作为场效应晶体管的一部分的变薄的半导体鳍片。

公开(公告)号：US20100148234A1

公开(公告)日：2010-06-17

申请号：US12713125

申请日：2010-02-25

申请人： Kevin J. Torek ,  Mark Fischer ,  Robert J. Hanson

发明人： Kevin J. Torek ,  Mark Fischer ,  Robert J. Hanson

IPC分类号： H01L27/06 ,  H01L29/78

CPC分类号： H01L29/7851 ,  H01L27/10808 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

摘要： Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic etch, at least in the channel region. In one implementation, the protrusion is contoured by a dry isotropic etch having excellent selectivity, using a downstream microwave plasma etch.

摘要翻译： 提供了新颖的蚀刻技术，用于在低于光刻分辨率极限的条件下成形硅特征。 FinFET器件通过凹陷氧化物和至少在沟道区域中将硅突起暴露于各向同性蚀刻来限定。 在一个实施方案中，使用下游微波等离子体蚀刻，通过具有优异选择性的干各向同性蚀刻来形成突起。

公开(公告)号：US20080086358A1

公开(公告)日：2008-04-10

申请号：US11832526

申请日：2007-08-01

申请人： Kedar Doshi ,  Mark Fischer ,  Evan Chou

发明人： Kedar Doshi ,  Mark Fischer ,  Evan Chou

IPC分类号： G06F17/30

CPC分类号： G06Q10/04 ,  G06Q10/0639 ,  G06Q30/0202

摘要： In accordance with embodiments, there are provided mechanisms and methods for selecting a synchronous or asynchronous process to determine a forecast. These mechanisms and methods for such synchronous/asynchronous process selection can enable embodiments to determine forecasts for multiple users (e.g. with hierarchical relationships, etc.) over an arbitrary time interval. The ability of embodiments to provide forecasts that involve such a large amount of data in an effective way can enable forecasting that was otherwise infeasible due to resource limitations.

摘要翻译： 根据实施例，提供了用于选择同步或异步过程以确定预测的机制和方法。 用于这种同步/异步过程选择的这些机制和方法可使得实施例能够在任意时间间隔上确定多个用户的预测（例如，具有层次关系等）。 实施例以有效的方式提供涉及这样大量数据的预测的能力可以使由于资源限制而导致的预测是不可行的。

公开(公告)号：US07119397B2

公开(公告)日：2006-10-10

申请号：US10768081

申请日：2004-02-02

申请人： Mark Fischer ,  Charles H. Dennison ,  Fawad Ahmed ,  Richard H. Lane ,  John K. Zahurak ,  Kunal R. Parekh

发明人： Mark Fischer ,  Charles H. Dennison ,  Fawad Ahmed ,  Richard H. Lane ,  John K. Zahurak ,  Kunal R. Parekh

IPC分类号： H01L29/06

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/28247 ,  H01L29/6656

摘要： A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.

摘要翻译： 公开了一种用于在诸如MOSFET访问装置的存储器阵列器件中形成扩散区的双层覆盖离子注入方法。 该方法提供了在其表面上形成栅极结构的半导体衬底。接下来，通过第一覆盖离子注入工艺在与沟道区相邻的区域中形成第一对扩散区。 第一次毯式离子注入工艺具有第一能级和剂量。 该器件经受氧化条件，其在栅极结构上形成氧化的侧壁。 在与第一离子注入工艺相同的位置处进行第二覆盖离子注入工艺，向扩散区域添加额外的掺杂剂。 第二次毯子离子注入过程具有第二能量水平和剂量。 所得到的扩散区域提供了比现有技术的装置更好的静态刷新性能的装置。 此外，第一和第二能量水平和剂量基本上低于现有技术单一植入过程中使用的能级和剂量。

公开(公告)号：US20050208733A1

公开(公告)日：2005-09-22

申请号：US11126102

申请日：2005-05-10

申请人： Zhiping Yin ,  Mark Fischer

发明人： Zhiping Yin ,  Mark Fischer

IPC分类号： H01L21/027 ,  H01L21/318 ,  H01L21/76

CPC分类号： H01L21/3105 ,  H01L21/0274 ,  H01L21/3185

摘要： The present invention includes a method for preventing distortion in semiconductor fabrication. The method comprises providing a substrate comprising a film comprising silicon nitride. The substrate is treated in a vacuum of about 3.0-6.5 Torr in an atmosphere comprising oxygen plasma wherein the oxygen plasma flow rate is at least about 300 sccm oxygen. A resist is applied to the treated substrate and the resist is patterned over the treated substrate.

摘要翻译： 本发明包括一种用于防止半导体制造中的变形的方法。 该方法包括提供包含含氮化硅的膜的衬底。 在包含氧等离子体的气氛中，在约3.0-6.5乇的真空中处理衬底，其中氧等离子体流速为至少约300sccm的氧气。 将抗蚀剂施加到经处理的基底上，并且将抗蚀剂图案化在经处理的基底上。

公开(公告)号：US06635530B2

公开(公告)日：2003-10-21

申请号：US09057148

申请日：1998-04-07

申请人： Mark A. Helm ,  Mark Fischer ,  John T. Moore ,  Scott Jeffrey DeBoer

发明人： Mark A. Helm ,  Mark Fischer ,  John T. Moore ,  Scott Jeffrey DeBoer

IPC分类号： H01L21336

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L29/511

摘要： The invention includes a method of forming a gated semiconductor assembly. A first transistor gate layer is formed over a substrate. A silicon nitride layer is formed over the first transistor gate layer. The silicon nitride layer comprises a first portion and a second portion elevationally displaced above the first portion. The first portion has less electrical resistance than the second portion and a different stoichiometric composition than the second portion. The first portion is physically against the second portion. A second transistor gate layer is formed over the silicon nitride layer.

摘要翻译： 本发明包括一种形成门控半导体组件的方法。 在衬底上形成第一晶体管栅极层。 在第一晶体管栅极层上形成氮化硅层。 氮化硅层包括第一部分和在第一部分上方向上移位的第二部分。 第一部分具有比第二部分更少的电阻和不同于第二部分的化学计量组成。 第一部分物理地抵靠第二部分。 在氮化硅层上形成第二晶体管栅极层。

公开(公告)号：US06605532B1

公开(公告)日：2003-08-12

申请号：US09858121

申请日：2001-05-15

申请人： Kunal R. Parekh ,  Mark Fischer ,  Charles H. Dennison

发明人： Kunal R. Parekh ,  Mark Fischer ,  Charles H. Dennison

IPC分类号： H01L214763

CPC分类号： H01L23/485 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

摘要： A network of electrically conductive plate contacts is provided within the structure of a DRAM chip to enable storage of non-zero voltage levels in each charge storage region. An improved cell or top plate contact provides low contact resistance and improved structural integrity making the contact less prone to removal during subsequent processing steps. A top plate conformally lines a container patterned down into a subregion. A metal contact structure comprises a waist section, a contact leg, and an anchor leg. The contact leg makes contact to the top plate within the container interior. The waist section joins the top of the contact leg to the top of the anchor leg and extends over the edge of the top plate. The anchor leg extends downward through the subregion adjacent to but spaced from the container to anchor the structure in place and provide structural integrity. Accordingly, the present invention provides an improved structure for contact to a conductive thin film, having low contact resistance and an improved structural integrity.

公开(公告)号：US06429151B1

公开(公告)日：2002-08-06

申请号：US09619468

申请日：2000-07-19

申请人： John T. Moore ,  Scott J. DeBoer ,  Mark Fischer

发明人： John T. Moore ,  Scott J. DeBoer ,  Mark Fischer

IPC分类号： H01L2131

CPC分类号： H01L21/3185 ,  H01L21/32 ,  H01L21/76202

摘要： In one aspect, the invention includes a method of semiconductive wafer processing comprising forming a silicon nitride layer over a surface of a semiconductive wafer, the silicon nitride layer comprising at least two portions, one of said at least two portions generating a compressive force against the other of the at least two portions, and the other of the at least two portions generating a tensile force against the one of the at least two portions. In another aspect, the invention includes a method of reducing stress on semiconductive wafer, the semiconductive wafer having a pair of opposing surfaces and having more silicon nitride over one of the opposing surfaces than over the other of the opposing surfaces, the method comprising providing the silicon nitride over the one of the opposing surfaces to comprise a first portion, a second portion and a third portion, the first, second and third portions being elevationally displaced relative to one another, the second portion being between the first and third portions, the second portion having a greater stoichiometric amount of silicon than the first and third portions, the semiconductive wafer being subjected to less stress than if the silicon nitride over the one of the opposing surfaces had a constant stoichiometric amount of silicon throughout its thickness. In yet other aspects, the invention includes semiconductive wafer assemblies.

摘要翻译： 在一个方面，本发明包括半导体晶片处理方法，包括在半导体晶片的表面上形成氮化硅层，所述氮化硅层包括至少两个部分，所述至少两个部分中的一个产生抵抗 所述至少两个部分中的另一个，并且所述至少两个部分中的另一部分产生相对于所述至少两个部分中的一个部分的张力。 在另一方面，本发明包括减少半导体晶片上的应力的方法，该半导体晶片具有一对相对的表面，并且在相对表面的一个之上具有比另一个相对表面更多的氮化硅，该方法包括提供 所述相对表面中的一个上的氮化硅包括第一部分，第二部分和第三部分，所述第一部分，第二部分和第三部分相对于彼此正向移位，所述第二部分位于第一部分和第三部分之间， 第二部分具有比第一和第三部分更大的化学计算量的硅，与相对表面上的一个相反的表面上的氮化硅在整个厚度上具有恒定的化学计量的硅时，半导体晶片受到的应力较小。 在另一方面，本发明包括半导体晶片组件。

公开(公告)号：US06372601B1

公开(公告)日：2002-04-16

申请号：US09146838

申请日：1998-09-03

申请人： David L. Dickerson ,  Richard H. Lane ,  Charles H. Dennison ,  Kunal R. Parekh ,  Mark Fischer ,  John K. Zahurak

发明人： David L. Dickerson ,  Richard H. Lane ,  Charles H. Dennison ,  Kunal R. Parekh ,  Mark Fischer ,  John K. Zahurak

IPC分类号： H01L21762

CPC分类号： H01L21/76232 ,  H01L21/0332 ,  H01L21/76235

摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.