公开(公告)号：US20120155308A1

公开(公告)日：2012-06-21

申请号：US13330572

申请日：2011-12-19

申请人： Je-Hun LEE ,  Sok-Kyu Lee

发明人： Je-Hun LEE ,  Sok-Kyu Lee

IPC分类号： H04W24/00 ,  H04L12/26

CPC分类号： H04W24/00 ,  H04W36/06 ,  H04W48/16 ,  H04W52/0206 ,  H04W88/08 ,  Y02D70/142

摘要： Disclosed is a method for controlling a plurality of access points by a monitoring station in a communication system, including: receiving access point status report policy information from a control server; receiving a basic service set load information element from the plurality of access points; generating access point status information by using the basic service set load information element; transmitting the access point status information to the control server by a method specified in the access point status report policy information; receiving an access point control command from the control server; and transmitting the access point control command to the plurality of access points.

摘要翻译： 公开了一种通信系统中的监控站控制多个接入点的方法，包括：从控制服务器接收接入点状态报告策略信息; 从所述多个接入点接收基本服务集负载信息元素; 通过使用基本服务集负载信息元素生成接入点状态信息; 通过接入点状态报告策略信息中指定的方法向接入点状态信息发送接入点状态信息; 从所述控制服务器接收接入点控制命令; 以及将所述接入点控制命令发送到所述多个接入点。

公开(公告)号：US20090163022A1

公开(公告)日：2009-06-25

申请号：US12369839

申请日：2009-02-12

申请人： Je-Hun LEE ,  Jae-Kyeong LEE ,  Chang-Oh JEONG ,  Beom-Seok CHO

发明人： Je-Hun LEE ,  Jae-Kyeong LEE ,  Chang-Oh JEONG ,  Beom-Seok CHO

IPC分类号： H01L21/4763

CPC分类号： H01L29/66765 ,  H01L27/12 ,  H01L29/458 ,  H01L29/4908

摘要： Multi-layered wiring for a larger flat panel display is formed by depositing molybdenum on a substrate in presence of a precursor gas containing at least one oxygen, nitrogen and carbon to form a molybdenum layer. An aluminum layer is deposited on the molybdenum layer. Another metal layer may be formed on the aluminum layer. The molybdenum layer has a face-centered cubic (FCC) lattice structure with a preferred orientation of (111).

摘要翻译： 在含有至少一个氧，氮和碳的前体气体的存在下，在基板上沉积钼以形成钼层，形成用于较大平板显示器的多层布线。 铝层沉积在钼层上。 可以在铝层上形成另一金属层。 钼层具有面心立方（FCC）晶格结构，其优选取向为（111）。

公开(公告)号：US20120315731A1

公开(公告)日：2012-12-13

申请号：US13523767

申请日：2012-06-14

申请人： Je-Hun LEE ,  Sung-Jin KIM ,  Hee-Joon KIM ,  Chang-Oh JEONG

发明人： Je-Hun LEE ,  Sung-Jin KIM ,  Hee-Joon KIM ,  Chang-Oh JEONG

IPC分类号： H01L21/336

CPC分类号： G02F1/13439 ,  G02F1/13458 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

摘要： A thin film transistor array panel is provided, which includes a plurality of gate line, a plurality of common electrodes, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer, a plurality of drain electrodes formed on the semiconductor layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn is not produced on the surfaces of the common electrode.

摘要翻译： 提供薄膜晶体管阵列面板，其包括多个栅极线，多个公共电极，覆盖栅极线和公共电极的栅极绝缘层，形成在栅极绝缘层上的多个半导体层，多个 包括多个源电极并形成在半导体层上的数据线，形成在半导体层上的多个漏电极以及与公共电极重叠并连接到漏电极的多个像素电极。 由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生不透明金属Sn或Zn。

公开(公告)号：US20110284836A1

公开(公告)日：2011-11-24

申请号：US13080413

申请日：2011-04-05

申请人： Je-Hun LEE ,  Jae-Woo PARK ,  Byung-Du AHN ,  Sei-Yong PARK ,  Jun-Hyun PARK

发明人： Je-Hun LEE ,  Jae-Woo PARK ,  Byung-Du AHN ,  Sei-Yong PARK ,  Jun-Hyun PARK

IPC分类号： H01L29/786

CPC分类号： H01L29/45 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

摘要： A thin-film transistor includes a gate electrode, a source electrode, a drain electrode, a gate insulation layer and an oxide semiconductor pattern. The source and drain electrodes include a first metal element with a first oxide formation free energy. The oxide semiconductor pattern has a first surface making contact with the gate insulation layer and a second surface making contact with the source and drain electrodes to be positioned at an opposite side of the first surface. The oxide semiconductor pattern includes an added element having a second oxide formation free energy having an absolute value greater than or equal to an absolute value of the first oxide formation free energy, wherein an amount of the added element included in a portion near the first surface is zero or smaller than an amount of the added element included in a portion near the second surface.

摘要翻译： 薄膜晶体管包括栅电极，源电极，漏电极，栅极绝缘层和氧化物半导体图案。 源极和漏极包括具有第一氧化物形成自由能的第一金属元件。 氧化物半导体图案具有与栅极绝缘层接触的第一表面和与源极和漏极电极接触以与第一表面相对的第二表面。 氧化物半导体图案包括具有绝对值大于或等于第一氧化物形成自由能的绝对值的第二氧化物形成自由能的添加元素，其中包括在第一表面附近的部分中的添加元素的量 为零或小于包含在靠近第二表面的部分中的添加元素的量。

公开(公告)号：US20090224254A1

公开(公告)日：2009-09-10

申请号：US12417280

申请日：2009-04-02

申请人： Je-Hun LEE ,  Sung-Jin Kim ,  Hee-Joon Kim ,  Chang-Oh Jeong

发明人： Je-Hun LEE ,  Sung-Jin Kim ,  Hee-Joon Kim ,  Chang-Oh Jeong

IPC分类号： H01L27/06 ,  H01L33/00 ,  H01L29/786

CPC分类号： G02F1/13439 ,  G02F1/13458 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

摘要： A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn in which the rmetal component is reduced in the IZO, ITO, or a-ITO is not produced on the surfaces of the common electrode.

摘要翻译： 提供了薄膜晶体管阵列面板，其包括基板，形成在基板上的多个栅极线，在基板上具有透明导电层的多个公共电极，覆盖栅极线和公共电极的栅极绝缘层 形成在所述栅极绝缘层上的多个半导体层，形成在所述半导体层和所述栅极绝缘层上的多个源极电极的多条数据线，形成在所述半导体层上的多个漏电极和所述栅极绝缘体 并且与公共电极重叠并连接到漏电极的多个像素电极。 由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生在IZO，ITO或ITO中还原金属成分的不透明金属Sn或Zn。

公开(公告)号：US20080138942A1

公开(公告)日：2008-06-12

申请号：US12031121

申请日：2008-02-14

申请人： Je-Hun LEE ,  Yang-Ho BAE ,  Beom-Seok CHO ,  Chang-Oh JEONG

发明人： Je-Hun LEE ,  Yang-Ho BAE ,  Beom-Seok CHO ,  Chang-Oh JEONG

IPC分类号： H01L21/336

CPC分类号： H01L27/3279 ,  H01L27/124 ,  H01L27/1288 ,  H01L51/0023 ,  H01L51/56

摘要： The invention provides a thin film transistor (TFT) array panel that includes an insulating substrate; a gate line formed on the insulating substrate and having a first layer of an Al containing metal, a second layer of a Cu containing metal that is thicker than the first layer, and a gate electrode; a gate insulating layer arranged on the gate line; a semiconductor arranged on the gate insulating layer; a data line having a source electrode and arranged on the gate insulating layer and the semiconductor; a drain electrode arranged on the gate insulating layer and the semiconductor and facing the source electrode; a passivation layer having a contact hole and arranged on the data line and the drain electrode; and a pixel electrode arranged on the passivation layer and coupled with the drain electrode through the contact hole.

摘要翻译： 本发明提供一种薄膜晶体管（TFT）阵列面板，其包括绝缘基板; 形成在所述绝缘基板上并具有含有Al的金属的第一层，比所述第一层更厚的含Cu金属的第二层的栅极线和栅电极; 栅极绝缘层，布置在栅极线上; 布置在栅绝缘层上的半导体; 数据线，其具有源电极并且布置在所述栅极绝缘层和所述半导体上; 布置在所述栅绝缘层和所述半导体上并面对所述源电极的漏电极; 钝化层，其具有接触孔并且布置在所述数据线和所述漏电极上; 以及设置在钝化层上并通过接触孔与漏电极耦合的像素电极。

公开(公告)号：US20120003796A1

公开(公告)日：2012-01-05

申请号：US13230111

申请日：2011-09-12

申请人： Je-Hun LEE ,  Young-Min KIM ,  Bo-Sung KIM ,  Jun-Young LEE ,  Sung-Wook KANG

发明人： Je-Hun LEE ,  Young-Min KIM ,  Bo-Sung KIM ,  Jun-Young LEE ,  Sung-Wook KANG

IPC分类号： H01L21/336

CPC分类号： H01L51/102 ,  G02F1/13439 ,  H01L27/283 ,  H01L51/0541 ,  H01L51/0545

摘要： An improved display substrate is provided to reduce surface defects on insulating layers of organic thin film transistors. Related methods of manufacture are also provided. In one example, a display substrate includes a base, a plurality of data lines, a plurality of gate lines, a pixel defined by the data lines and the gate lines, an organic thin film transistor, and a pixel electrode. The data lines are on the base and are oriented in a first direction. The gate lines are oriented in a second direction that crosses the first direction. The organic thin film transistor includes a source electrode electrically connected to one of the data lines, a gate electrode electrically connected to one of the gate lines, and an organic semiconductor layer. The pixel electrode is disposed in the pixel and electrically connected to the organic thin film transistor. The pixel electrode comprises a transparent oxynitride.

摘要翻译： 提供改进的显示基板以减少有机薄膜晶体管的绝缘层上的表面缺陷。 还提供了相关的制造方法。 在一个示例中，显示基板包括基底，多条数据线，多条栅极线，由数据线和栅极线限定的像素，有机薄膜晶体管和像素电极。 数据线在基座上并且朝向第一方向。 栅极线在与第一方向交叉的第二方向上取向。 有机薄膜晶体管包括电连接到数据线之一的源电极，电连接到栅极线之一的栅电极和有机半导体层。 像素电极设置在像素中并电连接到有机薄膜晶体管。 像素电极包括透明氧氮化物。

公开(公告)号：US20110284857A1

公开(公告)日：2011-11-24

申请号：US13204553

申请日：2011-08-05

申请人： Je-Hun LEE ,  Sung-Jin Kim ,  Hee-Joon Kim ,  Chang-Oh Jeong

发明人： Je-Hun LEE ,  Sung-Jin Kim ,  Hee-Joon Kim ,  Chang-Oh Jeong

IPC分类号： H01L27/088 ,  H01L21/84

CPC分类号： G02F1/13439 ,  G02F1/13458 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

摘要： A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn in which the rmetal component is reduced in the IZO, ITO, or a-ITO is not produced on the surfaces of the common electrode.

摘要翻译： 提供薄膜晶体管阵列面板，其包括基板，形成在基板上的多个栅极线，在基板上具有透明导电层的多个公共电极，覆盖栅极线和公共电极的栅极绝缘层 形成在所述栅极绝缘层上的多个半导体层，形成在所述半导体层和所述栅极绝缘层上的多个源极电极的多条数据线，形成在所述半导体层上的多个漏电极和所述栅极绝缘体 并且与公共电极重叠并连接到漏电极的多个像素电极。 由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生在IZO，ITO或ITO中还原金属成分的不透明金属Sn或Zn。

公开(公告)号：US20110065220A1

公开(公告)日：2011-03-17

申请号：US12951981

申请日：2010-11-22

申请人： Je-Hun LEE ,  Beom-Seok Cho ,  Chang-Oh Jeong ,  Joo-Han Kim

发明人： Je-Hun LEE ,  Beom-Seok Cho ,  Chang-Oh Jeong ,  Joo-Han Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/124 ,  H01L27/1288 ,  H01L29/12 ,  H01L29/458

摘要： The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode on the gate electrode; and a pixel electrode electrically connected to the drain electrode.

摘要翻译： 本发明提供一种薄膜晶体管阵列板，包括：绝缘基板; 形成在所述绝缘基板上并具有栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在栅极绝缘层上并与栅电极重叠的半导体; 在半导体上形成并含有氮的扩散阻挡层; 跨越栅极线并且具有部分地接触扩散阻挡层的源电极的数据线; 漏电极部分地接触扩散阻挡层并面对栅电极上的源电极; 以及电连接到漏电极的像素电极。

公开(公告)号：US20120112181A1

公开(公告)日：2012-05-10

申请号：US13103593

申请日：2011-05-09

申请人： Je-Hun LEE ,  Joo-Han KIM ,  Byung-Du AHN ,  Sang Wook KIM ,  Jae Woo PARK ,  Chang Jung KIM

发明人： Je-Hun LEE ,  Joo-Han KIM ,  Byung-Du AHN ,  Sang Wook KIM ,  Jae Woo PARK ,  Chang Jung KIM

IPC分类号： H01L29/12

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L29/41733

摘要： An oxide semiconductor including: (A) at least one element of zinc (Zn) and tin (Sn); and (B) at least one element of arsenic (As), antimony (Sb), chromium (Cr), cerium (Ce), tantalum (Ta), neodymium (Nd), niobium (Nb), scandium (Sc), yttrium (Y), and hafnium (Hf), is provided.

摘要翻译： 包括：（A）锌（Zn）和锡（Sn）的至少一种元素的氧化物半导体; 和（B）砷（As），锑（Sb），铬（Cr），铈（Ce），钽（Ta），钕（Nd），铌（Nb），钪（Sc） （Y）和铪（Hf）。