公开(公告)号：US20110065220A1

公开(公告)日：2011-03-17

申请号：US12951981

申请日：2010-11-22

申请人： Je-Hun LEE ,  Beom-Seok Cho ,  Chang-Oh Jeong ,  Joo-Han Kim

发明人： Je-Hun LEE ,  Beom-Seok Cho ,  Chang-Oh Jeong ,  Joo-Han Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/124 ,  H01L27/1288 ,  H01L29/12 ,  H01L29/458

摘要： The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode on the gate electrode; and a pixel electrode electrically connected to the drain electrode.

摘要翻译： 本发明提供一种薄膜晶体管阵列板，包括：绝缘基板; 形成在所述绝缘基板上并具有栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在栅极绝缘层上并与栅电极重叠的半导体; 在半导体上形成并含有氮的扩散阻挡层; 跨越栅极线并且具有部分地接触扩散阻挡层的源电极的数据线; 漏电极部分地接触扩散阻挡层并面对栅电极上的源电极; 以及电连接到漏电极的像素电极。

公开(公告)号：US20090163022A1

公开(公告)日：2009-06-25

申请号：US12369839

申请日：2009-02-12

申请人： Je-Hun LEE ,  Jae-Kyeong LEE ,  Chang-Oh JEONG ,  Beom-Seok CHO

发明人： Je-Hun LEE ,  Jae-Kyeong LEE ,  Chang-Oh JEONG ,  Beom-Seok CHO

IPC分类号： H01L21/4763

CPC分类号： H01L29/66765 ,  H01L27/12 ,  H01L29/458 ,  H01L29/4908

摘要： Multi-layered wiring for a larger flat panel display is formed by depositing molybdenum on a substrate in presence of a precursor gas containing at least one oxygen, nitrogen and carbon to form a molybdenum layer. An aluminum layer is deposited on the molybdenum layer. Another metal layer may be formed on the aluminum layer. The molybdenum layer has a face-centered cubic (FCC) lattice structure with a preferred orientation of (111).

摘要翻译： 在含有至少一个氧，氮和碳的前体气体的存在下，在基板上沉积钼以形成钼层，形成用于较大平板显示器的多层布线。 铝层沉积在钼层上。 可以在铝层上形成另一金属层。 钼层具有面心立方（FCC）晶格结构，其优选取向为（111）。

公开(公告)号：US20100022041A1

公开(公告)日：2010-01-28

申请号：US12576217

申请日：2009-10-08

申请人： Je-Hun LEE ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

发明人： Je-Hun LEE ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

IPC分类号： H01L21/16

CPC分类号： H01L27/1214 ,  H01L27/1225 ,  H01L27/124

摘要： The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

摘要翻译： 本发明提供一种薄膜晶体管阵列板，其包括绝缘基板; 形成在所述绝缘基板上的栅极线; 栅极绝缘层，形成在栅极线上; 漏电极和数据线，其具有形成在所述栅极绝缘层上的源电极，所述漏电极与所述源电极相邻，其间具有间隙; 以及耦合到所述漏电极的像素电极，其中所述栅极线，所述数据线和所述漏电极中的至少一个包括包括导电氧化物的第一导电层和包含铜（Cu）的第二导电层。

公开(公告)号：US20080138942A1

公开(公告)日：2008-06-12

申请号：US12031121

申请日：2008-02-14

申请人： Je-Hun LEE ,  Yang-Ho BAE ,  Beom-Seok CHO ,  Chang-Oh JEONG

发明人： Je-Hun LEE ,  Yang-Ho BAE ,  Beom-Seok CHO ,  Chang-Oh JEONG

IPC分类号： H01L21/336

CPC分类号： H01L27/3279 ,  H01L27/124 ,  H01L27/1288 ,  H01L51/0023 ,  H01L51/56

摘要： The invention provides a thin film transistor (TFT) array panel that includes an insulating substrate; a gate line formed on the insulating substrate and having a first layer of an Al containing metal, a second layer of a Cu containing metal that is thicker than the first layer, and a gate electrode; a gate insulating layer arranged on the gate line; a semiconductor arranged on the gate insulating layer; a data line having a source electrode and arranged on the gate insulating layer and the semiconductor; a drain electrode arranged on the gate insulating layer and the semiconductor and facing the source electrode; a passivation layer having a contact hole and arranged on the data line and the drain electrode; and a pixel electrode arranged on the passivation layer and coupled with the drain electrode through the contact hole.

摘要翻译： 本发明提供一种薄膜晶体管（TFT）阵列面板，其包括绝缘基板; 形成在所述绝缘基板上并具有含有Al的金属的第一层，比所述第一层更厚的含Cu金属的第二层的栅极线和栅电极; 栅极绝缘层，布置在栅极线上; 布置在栅绝缘层上的半导体; 数据线，其具有源电极并且布置在所述栅极绝缘层和所述半导体上; 布置在所述栅绝缘层和所述半导体上并面对所述源电极的漏电极; 钝化层，其具有接触孔并且布置在所述数据线和所述漏电极上; 以及设置在钝化层上并通过接触孔与漏电极耦合的像素电极。

公开(公告)号：US20120315731A1

公开(公告)日：2012-12-13

申请号：US13523767

申请日：2012-06-14

申请人： Je-Hun LEE ,  Sung-Jin KIM ,  Hee-Joon KIM ,  Chang-Oh JEONG

发明人： Je-Hun LEE ,  Sung-Jin KIM ,  Hee-Joon KIM ,  Chang-Oh JEONG

IPC分类号： H01L21/336

CPC分类号： G02F1/13439 ,  G02F1/13458 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

摘要： A thin film transistor array panel is provided, which includes a plurality of gate line, a plurality of common electrodes, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer, a plurality of drain electrodes formed on the semiconductor layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn is not produced on the surfaces of the common electrode.

摘要翻译： 提供薄膜晶体管阵列面板，其包括多个栅极线，多个公共电极，覆盖栅极线和公共电极的栅极绝缘层，形成在栅极绝缘层上的多个半导体层，多个 包括多个源电极并形成在半导体层上的数据线，形成在半导体层上的多个漏电极以及与公共电极重叠并连接到漏电极的多个像素电极。 由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生不透明金属Sn或Zn。

公开(公告)号：US20110140103A1

公开(公告)日：2011-06-16

申请号：US13030213

申请日：2011-02-18

申请人： Je-Hun LEE ,  Do-Hyun KIM ,  Eun-Guk LEE ,  Chang-OH JEONG

发明人： Je-Hun LEE ,  Do-Hyun KIM ,  Eun-Guk LEE ,  Chang-OH JEONG

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/7869 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288

摘要： A thin-film transistor includes a semiconductor pattern, source and drain electrodes and a gate electrode, the semiconductor pattern is formed on a base substrate, and the semiconductor pattern includes metal oxide. The source and drain electrodes are formed on the semiconductor pattern such that the source and drain electrodes are spaced apart from each other and an outline of the source and drain electrodes is substantially same as an outline of the semiconductor pattern. The gate electrode is disposed in a region between the source and drain electrodes such that portions of the gate electrode are overlapped with the source and drain electrodes. Therefore, leakage current induced by light is minimized. As a result, characteristics of the thin-film transistor are enhanced, after-image is reduced to enhance display quality, and stability of manufacturing process is enhanced.

摘要翻译： 薄膜晶体管包括半导体图案，源极和漏极以及栅极，半导体图案形成在基底基板上，半导体图案包括金属氧化物。 源极和漏极形成在半导体图案上，使得源极和漏极彼此间隔开，并且源极和漏极的轮廓与半导体图案的轮廓基本相同。 栅电极设置在源电极和漏电极之间的区域中，使得栅电极的一部分与源电极和漏电极重叠。 因此，由光引起的漏电流最小化。 结果，增强了薄膜晶体管的特性，减少了后图像以提高显示质量，并且提高了制造工艺的稳定性。

公开(公告)号：US20090224254A1

公开(公告)日：2009-09-10

申请号：US12417280

申请日：2009-04-02

申请人： Je-Hun LEE ,  Sung-Jin Kim ,  Hee-Joon Kim ,  Chang-Oh Jeong

发明人： Je-Hun LEE ,  Sung-Jin Kim ,  Hee-Joon Kim ,  Chang-Oh Jeong

IPC分类号： H01L27/06 ,  H01L33/00 ,  H01L29/786

CPC分类号： G02F1/13439 ,  G02F1/13458 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

摘要： A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn in which the rmetal component is reduced in the IZO, ITO, or a-ITO is not produced on the surfaces of the common electrode.

摘要翻译： 提供了薄膜晶体管阵列面板，其包括基板，形成在基板上的多个栅极线，在基板上具有透明导电层的多个公共电极，覆盖栅极线和公共电极的栅极绝缘层 形成在所述栅极绝缘层上的多个半导体层，形成在所述半导体层和所述栅极绝缘层上的多个源极电极的多条数据线，形成在所述半导体层上的多个漏电极和所述栅极绝缘体 并且与公共电极重叠并连接到漏电极的多个像素电极。 由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生在IZO，ITO或ITO中还原金属成分的不透明金属Sn或Zn。

公开(公告)号：US20080308826A1

公开(公告)日：2008-12-18

申请号：US11930502

申请日：2007-10-31

申请人： Je-Hun LEE ,  Do-Hyun KIM ,  Eun-Guk LEE ,  Chang-Oh JEONG

发明人： Je-Hun LEE ,  Do-Hyun KIM ,  Eun-Guk LEE ,  Chang-Oh JEONG

IPC分类号： H01L29/78 ,  H01L21/02

CPC分类号： H01L29/7869 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288

摘要： A thin-film transistor includes a semiconductor pattern, source and drain electrodes and a gate electrode, the semiconductor pattern is formed on a base substrate, and the semiconductor pattern includes metal oxide. The source and drain electrodes are formed on the semiconductor pattern such that the source and drain electrodes are spaced apart from each other and an outline of the source and drain electrodes is substantially same as an outline of the semiconductor pattern. The gate electrode is disposed in a region between the source and drain electrodes such that portions of the gate electrode are overlapped with the source and drain electrodes. Therefore, leakage current induced by light is minimized. As a result, characteristics of the thin-film transistor are enhanced, after-image is reduced to enhance display quality, and stability of manufacturing process is enhanced.

摘要翻译： 薄膜晶体管包括半导体图案，源极和漏极以及栅极，半导体图案形成在基底基板上，半导体图案包括金属氧化物。 源极和漏极形成在半导体图案上，使得源极和漏极彼此间隔开，并且源极和漏极的轮廓与半导体图案的轮廓基本相同。 栅电极设置在源电极和漏电极之间的区域中，使得栅电极的一部分与源电极和漏电极重叠。 因此，由光引起的漏电流最小化。 结果，增强了薄膜晶体管的特性，减少了后图像以提高显示质量，并且提高了制造工艺的稳定性。

公开(公告)号：US20070236641A1

公开(公告)日：2007-10-11

申请号：US11695751

申请日：2007-04-03

申请人： Hong-Long NING ,  Chang-Oh JEONG ,  Je-Hun LEE ,  Do-Hyun KIM ,  Sung-Hen CHO ,  Ki-Yong SONG ,  Chang-Ho NOH

发明人： Hong-Long NING ,  Chang-Oh JEONG ,  Je-Hun LEE ,  Do-Hyun KIM ,  Sung-Hen CHO ,  Ki-Yong SONG ,  Chang-Ho NOH

IPC分类号： G02F1/1343

CPC分类号： G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295

摘要： A method of fabricating a thin film transistor (TFT) substrate includes forming a gate line and a data line on an insulating substrate. The data line crosses the gate line and is insulated from the gate line. The formation of the gate line, the data line, or both the gate line and the data line includes forming a low-resistive conductive pattern on a base pattern using an electroless plating method.

摘要翻译： 制造薄膜晶体管（TFT）基板的方法包括在绝缘基板上形成栅极线和数据线。 数据线与栅极线交叉并与栅极线绝缘。 栅极线，数据线或栅极线和数据线两者的形成包括使用化学镀方法在基底图案上形成低电阻导电图案。

公开(公告)号：US20110284857A1

公开(公告)日：2011-11-24

申请号：US13204553

申请日：2011-08-05

申请人： Je-Hun LEE ,  Sung-Jin Kim ,  Hee-Joon Kim ,  Chang-Oh Jeong

发明人： Je-Hun LEE ,  Sung-Jin Kim ,  Hee-Joon Kim ,  Chang-Oh Jeong

IPC分类号： H01L27/088 ,  H01L21/84

CPC分类号： G02F1/13439 ,  G02F1/13458 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

摘要： A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn in which the rmetal component is reduced in the IZO, ITO, or a-ITO is not produced on the surfaces of the common electrode.

摘要翻译： 提供薄膜晶体管阵列面板，其包括基板，形成在基板上的多个栅极线，在基板上具有透明导电层的多个公共电极，覆盖栅极线和公共电极的栅极绝缘层 形成在所述栅极绝缘层上的多个半导体层，形成在所述半导体层和所述栅极绝缘层上的多个源极电极的多条数据线，形成在所述半导体层上的多个漏电极和所述栅极绝缘体 并且与公共电极重叠并连接到漏电极的多个像素电极。 由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生在IZO，ITO或ITO中还原金属成分的不透明金属Sn或Zn。