公开(公告)号：US06775640B1

公开(公告)日：2004-08-10

申请号：US09560189

申请日：2000-04-28

申请人： Jeffrey C. Swanson ,  John A. Wickeraad

发明人： Jeffrey C. Swanson ,  John A. Wickeraad

IPC分类号： G06F742

CPC分类号： G06F11/348 ,  G06F2201/88

摘要： A performance adder for providing a running total of performance values within an integrated circuit chip. The performance adder is triggered by various performance events as determined through multiplexer logic for detecting occurrence of a particular performance event. The multiplexer logic can also trigger the performance adder through atomic, edge, toggle, or on/off signals related to the performance events or through a logical function of a combination of performance events. The performance adders can be used to compute average latency of a component in the circuit.

摘要翻译： 一种性能加法器，用于在集成电路芯片内提供运行中的性能值总计。 性能加法器由通过多路复用器逻辑确定的各种性能事件触发，用于检测特定性能事件的发生。 复用器逻辑还可以通过与性能事件相关的原子，边沿，触发或开/关信号或通过性能事件的组合的逻辑功能来触发性能加法器。 性能加法器可用于计算电路中组件的平均延迟。

公开(公告)号：US06662313B1

公开(公告)日：2003-12-09

申请号：US09563059

申请日：2000-04-29

申请人： Jeffrey C. Swanson ,  Sharon M. Ebner ,  John A. Wickeraad

发明人： Jeffrey C. Swanson ,  Sharon M. Ebner ,  John A. Wickeraad

IPC分类号： G06F1100

CPC分类号： G01R31/318522

摘要： Test circuitry is incorporated on a chip die together with a circuit to be tested, such as an ASIC or microprocessor, to provide external access to signals that are internal to an integrated circuit chip package. A test device includes a state machine responsive to (i) an arm command for transitioning from a standby state to an armed state, (ii) a final trigger event for transitioning from the armed state to a triggered state, and (iii) a post trigger count event for transitioning from the triggered state to the standby state. A controller provides the arm command and issues appropriate configuration controls to collect signal samples. In particular, a network responds to these commands from the controller to selectively provide signal samples from a device under test. A trigger event generator responds to logic or other characteristics of the signal samples to provide trigger events. These trigger events are counted by a trigger event counter in the armed state of the state machine to identify the final trigger event corresponding to an occurrence of a programmable number of the trigger events. A store event generator also responds to a programmed characteristic or combination(s) of the signal samples to provide a store event. Either or both of the event generators may use a mask to provide these events. A post trigger sample counter operates in the triggered state to provide the post trigger count event in response to a programmable number of signal samples being captured. A memory operates in the triggered state to store the samples being captured. The memory may optionally store samples in the armed state which occur prior to the targeted samples so as to provide test data from cycles prior to the targeted events.

摘要翻译： 测试电路与要测试的电路（例如ASIC或微处理器）一起并入芯片管芯，以提供对集成电路芯片封装内部的信号的外部访问。 测试装置包括响应于（i）从待机状态转移到武装状态的臂命令的状态机，（ii）从武装状态转换到触发状态的最终触发事件，以及（iii） 触发计数事件从触发状态转换到待机状态。 控制器提供arm命令并发出适当的配置控制来收集信号样本。 特别地，网络响应来自控制器的这些命令，以选择性地提供来自被测器件的信号样本。 触发事件发生器响应信号样本的逻辑或其他特性以提供触发事件。 这些触发事件由处于状态机的布防状态的触发事件计数器进行计数，以识别对应于触发事件的可编程数量的发生的最终触发事件。 存储事件发生器还响应编程的特征或信号样本的组合以提供存储事件。 事件发生器中的一个或两个可以使用掩码来提供这些事件。 后触发采样计数器在触发状态下操作以响应于可捕获的可编程数量的信号样本来提供后触发计数事件。 存储器在触发状态下操作以存储被捕获的样本。 存储器可以可选地存储在目标样本之前发生的布防状态的样本，以便在目标事件之前的周期提供测试数据。

公开(公告)号：US06591332B1

公开(公告)日：2003-07-08

申请号：US09561332

申请日：2000-04-28

申请人： Jeffrey C. Swanson ,  John A. Wickeraad

发明人： Jeffrey C. Swanson ,  John A. Wickeraad

IPC分类号： G06F1200

CPC分类号： G06F12/121 ,  G06F12/0891

摘要： An apparatus and method using a valid bit in a cache entry address first-in-first-out (FIFO) to indicate when a cache entry can be flushed in a coherent memory domain. One embodiment of the invention involves a method for tracking a cache entry in a cache serving data transfers between a coherent memory domain and a non-coherent memory domain in a data processing system, including steps of storing an address corresponding to a cache entry in a FIFO register, using at least one register cell as a valid flag to indicate when the cache entry is still in the cache, and changing the valid flag based on one or more signals transmitted from the non-coherent memory domain. A second embodiment of the invention involves a data processing system or an I/O bridge host, having a cache and multiple cache entries, serving data transfers between a coherent memory domain and a non-coherent memory domain, including registers configured to store an address corresponding to a cache entry, wherein each FIFO register has a valid flag to indicate when the cache entry is still in the cache, and the valid flag can be changed based on one or more signals transmitted from the non-coherent memory domain.

摘要翻译： 一种使用高速缓存入口地址中的先进先出（FIFO）中的有效位以指示何时可以在一个相干存储器域中刷新高速缓存条目的装置和方法。 本发明的一个实施例涉及一种用于跟踪缓存中的高速缓存条目的方法，该高速缓存用于数据处理系统中的相干存储器域和非相干存储器域之间的数据传输，包括以下步骤：将对应于高速缓存条目的地址存储在 FIFO寄存器，使用至少一个寄存器单元作为有效标志来指示高速缓存条目何时仍然在高速缓存中，以及基于从非相干存储器域发送的一个或多个信号来改变有效标志。 本发明的第二实施例涉及一种数据处理系统或具有高速缓存和多个高速缓存条目的I / O桥主机，用于在相干存储器域和非相干存储器域之间进行数据传输，包括被配置为存储地址的寄存器 对应于高速缓存条目，其中每个FIFO寄存器具有用于指示高速缓存条目何时仍然在高速缓存中的有效标志，并且可以基于从非相干存储器域发送的一个或多个信号来改变有效标志。

公开(公告)号：US5944843A

公开(公告)日：1999-08-31

申请号：US918696

申请日：1997-08-21

申请人： Debendra Das Sharma ,  John A. Wickeraad

发明人： Debendra Das Sharma ,  John A. Wickeraad

IPC分类号： H04L29/00 ,  H04L1/00 ,  H04L1/16 ,  H04L12/56 ,  H04L29/06 ,  H04L29/08 ,  G06F11/00

CPC分类号： H04L29/06 ,  H04L1/0057 ,  H04L1/0083 ,  H04L1/1671 ,  H04L47/35 ,  H04L1/16 ,  H04L2001/0095 ,  H04L69/22 ,  H04L69/324

摘要： A method and apparatus in accordance with the present invention uses the unused bits of a data packet to transmit additional information by piggy-backing "secondary" code words into a data packet containing a "primary" code word. A secondary code word may be piggy-backed into a data packet containing a primary code word when the primary code word and any secondary code words already stored in the data packet leave sufficient unused space in the data packet to store an additional secondary code word, and the route traveled by the data packet as the packet is routed to the network node addressed by the primary code passes through (or ends at) the network node addressed by the secondary code word, or passes through (or ends at) a network node that can relay the secondary code word to the network node addressed by the secondary code word. In a first embodiment, an ECC is generated for the primary code word using a predefined bit pattern (such as all 0's) for any unused bit positions in the data packet. The same predefined bit pattern is used for the unused bit positions when the integrity of the primary code word is verified at the destination. If it is desired to protect the secondary code word, a secondary ECC must also be stored in the data packet. In a second embodiment, the ECC is recalculated when a secondary code word is piggy-backed into the unused bit positions of the data packet. In this embodiment, the ECC associated with the data packet protects all data in the packet, including the primary and secondary code words.

摘要翻译： 根据本发明的方法和装置使用数据分组的未使用的比特通过捎带“次”码字来发送附加信息到包含“主”码字的数据分组中。 当主代码字和已经存储在数据分组中的任何辅助代码字在数据分组中留下足够的未使用空间以存储额外的辅助代码字时，副代码字可以被捎带到包含主代码字的数据分组中， 并且当分组被路由到由主代码寻址的网络节点时由数据分组传播的路由通过（或在其结束于）由第二代码字寻址的网络节点，或者通过（或最终）网络节点 可以将次要码字中继到由二次码字寻址的网络节点。 在第一实施例中，为数据分组中的任何未使用位位置使用预定义位模式（例如全0）为主代码字生成ECC。 当在目的地验证主码字的完整性时，相同的预定位位模式用于未使用的位位置。 如果希望保护辅助码字，则辅助ECC也必须存储在数据包中。 在第二实施例中，当第二码字被捎带到数据包的未使用位位置时，重新计算ECC。 在该实施例中，与数据分组相关联的ECC保护分组中的所有数据，包括主要和次要代码字。

公开(公告)号：US4789874A

公开(公告)日：1988-12-06

申请号：US77575

申请日：1987-07-23

申请人： Mark W. Majette ,  William J. Walsh ,  John A. Wickeraad

发明人： Mark W. Majette ,  William J. Walsh ,  John A. Wickeraad

IPC分类号： B41J19/18 ,  B41J2/51 ,  B41J19/20 ,  G01D5/245 ,  G01D5/36 ,  G05B19/23 ,  G05D3/12 ,  G06K15/22 ,  G01D15/24

CPC分类号： G05B19/231 ,  B41J19/202 ,  G01D5/2457 ,  G06K15/22 ,  G05B2219/37153 ,  G05B2219/37296 ,  G05B2219/42118 ,  G05B2219/42237 ,  G05B2219/43008 ,  G05B2219/45187

摘要： A control system providing a control of position, velocity, and direction of movement of a member in an axis of freedom which employs a scale having scale divisions thereon and bands or zones defining limits of constant velocity control, acceleration and deceleration zone limits, and a rest or parking position. The scale spans and parallels the axis of freedom. A single channel transducer or encoder mounted on and moving with the member produces time varying output signals in response to the sensing of scale divisions along the scale and signals of different characteristic in response to encoder sensing of the limit bands. The time varying output signals are employed as scale division count signals for position determination and as scale division count signals per unit of time, for velocity feedback. The signals of different characteristic produced upon entering and during crossing of the limit bands, are utilized in a system of logic for computing control system signals to compensate control uncertainties in differing functional modes of the control system.

公开(公告)号：US07852653B2

公开(公告)日：2010-12-14

申请号：US11810124

申请日：2007-06-04

申请人： John A. Wickeraad ,  Mark Gooch

发明人： John A. Wickeraad ,  Mark Gooch

IPC分类号： G11C15/00

CPC分类号： G11C15/00 ,  G06F7/74

摘要： Systems, devices, and methods, including executable instructions are provided for content addressable memory (CAM). One method includes defining the CAM into an array of data words having M rows and N columns, with each of N and M being greater than one. The data words of the CAM are arranged according to a 2-dimensional priority scheme. Data words outside a selected 1×M column are masked to be ignored in determining a match, and the CAM is searched. Each search includes N compare cycles and each compare cycle having a different 1×M column selected. A highest priority match per compare cycle is pipelined from a priority encoder with the pipelined matches arranged to communicate a priority order in a first dimension of the 2-dimensional priority scheme.

摘要翻译： 为内容可寻址存储器（CAM）提供系统，设备和方法，包括可执行指令。 一种方法包括将CAM定义为具有M行和N列的数据字阵列，其中N和M中的每一个大于1。 CAM的数据字根据二维优先级方案进行排列。 选定的1×M列之外的数据字在确定匹配时被屏蔽以被忽略，并且搜索CAM。 每个搜索包括N个比较周期，并且每个比较周期选择不同的1×M列。 每个比较周期的最高优先级匹配从优先编码器流水线化，其中流水线匹配被布置为在二维优先级方案的第一维度中传送优先级顺序。

公开(公告)号：US07469356B2

公开(公告)日：2008-12-23

申请号：US11063274

申请日：2005-02-22

申请人： John A. Wickeraad

发明人： John A. Wickeraad

IPC分类号： G06F1/12 ,  G06F1/04 ,  G06F5/00

CPC分类号： G01R31/31727 ,  G06F11/3632 ,  G06F11/3648

摘要： Methods, systems, and circuits are provided for signals crossing multiple clock domains. One circuit includes a number of different clock domains located on different portions of the ASIC. A number of input/output (I/O) ports are provided to couple signals to and from the ASIC. The circuit includes means for moving internal signals from a subset of the number of different clock domains of multiple frequencies to a different clock domain for monitoring, observation, counting, and debug.

摘要翻译： 为跨越多个时钟域的信号提供了方法，系统和电路。 一个电路包括位于ASIC的不同部分上的多个不同的时钟域。 提供多个输入/输出（I / O）端口以将信号耦合到ASIC和从ASIC耦合信号。 电路包括用于将来自多个频率的不同时钟域的数量的子集的内部信号移动到用于监视，观察，计数和调试的不同时钟域的装置。

公开(公告)号：US07266744B2

公开(公告)日：2007-09-04

申请号：US11011232

申请日：2004-12-14

申请人： Joseph A. Curcio, Jr. ,  John A. Wickeraad

发明人： Joseph A. Curcio, Jr. ,  John A. Wickeraad

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/31725 ,  G06F11/3409 ,  G06F2201/88

摘要： Application specific integrated circuits (ASICs) and methods are provided which allow for internal testing of an ASIC. One ASIC embodiment includes a processor on the ASIC. A memory is coupled to the processor. A test circuit is integrated on the ASIC and coupled to the processor to perform testing internal to the ASIC, the test circuit having an input to receive signals from the processor. The processor can read an output of the test circuit to determine a performance speed of the ASIC.

摘要翻译： 提供专用集成电路（ASIC）和方法，允许对ASIC进行内部测试。 一个ASIC实施例包括ASIC上的处理器。 存储器耦合到处理器。 测试电路集成在ASIC上并耦合到处理器以在ASIC内部进行测试，测试电路具有用于从处理器接收信号的输入。 处理器可以读取测试电路的输出，以确定ASIC的性能速度。

公开(公告)号：US06718454B1

公开(公告)日：2004-04-06

申请号：US09563060

申请日：2000-04-29

申请人： Sharon M. Ebner ,  John A. Wickeraad

发明人： Sharon M. Ebner ,  John A. Wickeraad

IPC分类号： G06F1200

CPC分类号： G06F12/0215 ,  G06F12/0862 ,  G06F13/161 ,  G06F2212/6022

摘要： A data processing system includes a memory storing data to be retrieved and an I/O controller configured to request data stored in the memory at a plurality of addresses. The I/O may be responsive to an internal or external device requesting such data. A fetch machine provides or initiates retrieval of data stored at the requested address, while a prefetch machine predicts future requests and keeps track of memory requests already initiated and queued. Thus, the prefetch machine is responsive to the plurality addresses to predict others of the addresses and provide or initiate retrieval of data stored thereat. To avoid prefetching information already requested and in a fetch queue, the prefetch machine includes a memory storing a last one of the addresses subject to prefetching. Finally, to avoid conflicts between currently requested data and prefetch operation, an arbiter resolves memory accesses or data requests initiated by the fetch and prefetch machines.

摘要翻译： 数据处理系统包括存储要被检索的数据的存储器和被配置为以多个地址请求存储在存储器中的数据的I / O控制器。 I / O可以响应于请求这样的数据的内部或外部设备。 提取机器提供或启动对在请求的地址处存储的数据的检索，而预取机器预测未来请求并且跟踪已经发起和排队的存储器请求。 因此，预取机器响应于多个地址来预测其他地址，并提供或启动对其上存储的数据的检索。 为了避免预取已经请求的信息并且在获取队列中，预取机器包括存储存储预取的最后一个地址的存储器。 最后，为了避免当前请求的数据和预取操作之间的冲突，仲裁器解决由获取和预取机器发起的内存访问或数据请求。

公开(公告)号：US06651180B1

公开(公告)日：2003-11-18

申请号：US09560551

申请日：2000-04-28

申请人： John A. Wickeraad

发明人： John A. Wickeraad

IPC分类号： G06F104

CPC分类号： G06F11/0757 ,  G06F12/0802

摘要： A timeout mechanism that can accommodate an improved accuracy in determining the timeout of a pending transaction while conserving the amount of processing circuitry is herein disclosed. A fetch state machine is associated with each cache line. When the cache line is fetched from memory, the fetch state machine tracks the number of timeout periods that lapse before the cache line is retrieved. If a predetermined number of timeout periods lapses before the cache line is retrieved, a timeout occurs and processed accordingly.

摘要翻译： 这里公开了一种超时机制，其可以适应在确定待处理事务的超时的改进的准确性的同时节省处理电路的数量。 获取状态机与每个高速缓存行相关联。 当从存储器中取出高速缓存行时，提取状态机跟踪在检索高速缓存行之前经过的超时周期数。 如果在检索高速缓存行之前经过预定数量的超时时间，则发生超时并相应地进行处理。