公开(公告)号：US06987597B2

公开(公告)日：2006-01-17

申请号：US10779237

申请日：2004-02-13

Applicant: Gregory J. Hewlett ,  Donald B. Doherty

Inventor： Gregory J. Hewlett ,  Donald B. Doherty

IPC: G02B26/00 ,  G02F1/01

CPC classification number: G09G3/342 ,  G09G3/2022 ,  G09G3/34 ,  G09G3/3413 ,  G09G5/02 ,  G09G2310/0235 ,  G09G2310/024 ,  G09G2310/061 ,  G09G2310/08 ,  H04N9/3117

Abstract: A system and method for addressing and synchronizing a spatial light modulator (SLM) device and a scrolling color recovery (SCR) illumination system. This method applies all the colors to a single SLM simultaneously and recaptures light rejected by the color filters. The recaptured light is reapplied to the color filters and, if passed by the color filter, directed to the SLM The SCR concept requires multiple colors to be imaged on to an SLM array simultaneously. As the color bands scroll across the SLM, the data applied to elements of the SLM changes to remain appropriate for the color being received by that element. The data a lied to the SLM elements ma be loaded into the SLM by reset group with each reset group load delayed by a skew time relative to the previous group.

Abstract translation: 用于寻址和同步空间光调制器（SLM）设备和滚动颜色恢复（SCR）照明系统的系统和方法。 该方法将所有颜色同时应用于单个SLM，并重新捕获由滤色片拒绝的光。 重新捕获的光被重新应用于滤色器，并且如果通过滤色器被引导到SLM。SCR概念要求将多种颜色同时映像到SLM阵列上。 当色带在SLM上滚动时，应用于SLM的元素的数据将更改为对该元素接收的颜色保持适当。 SLM元件的数据可以通过复位组加载到SLM中，每个复位组负载相对于前一组延迟了一个偏移时间。

公开(公告)号：US06898019B2

公开(公告)日：2005-05-24

申请号：US10779240

申请日：2004-02-13

Applicant: Gregory J. Hewlett ,  Donald B. Doherty

Inventor： Gregory J. Hewlett ,  Donald B. Doherty

IPC: G09G3/20 ,  G09G3/34 ,  G09G5/02 ,  H04N9/31 ,  G02B27/00

CPC classification number: G09G3/342 ,  G09G3/2022 ,  G09G3/34 ,  G09G3/3413 ,  G09G5/02 ,  G09G2310/0235 ,  G09G2310/024 ,  G09G2310/061 ,  G09G2310/08 ,  H04N9/3117

Abstract: An electronic method for addressing and synchronizing a spatial light modulator (SLM) device when used with color scrolling recovery (SCR) illumination. This method applies all the colors to a single SLM simultaneously and recaptures secondary light, redirecting it along the primary color paths to significantly improve the brightness in single-chip display applications. The SCR concept requires multiple colors to be imaged on to an SLM array simultaneously. This requires that the SLM be divided into reset groups so that separate groups of pixels can project bits from the different colors at the same time. As these color bands 602, 604, 606 scroll across the array, the various reset groups tracks these regions and change content to match. The method requires that the device be divided and controlled at an independent reset group level, with each group being delayed by a group_skew time 608 from the previous group. This method assures that all colors are exactly on the SLM at the same time, so that the color mix is the same at all times to assure good color intensities. Finally, the light during the transition time between colors bands, called spokes 1010, is added together as white light that further increases the brightness of the system.

Abstract translation: 当与彩色滚动恢复（SCR）照明一起使用时，用于寻址和同步空间光调制器（SLM）装置的电子方法。 该方法将所有颜色同时应用于单个SLM，并重新捕获二次光，将其沿着原色路径重定向，以显着提高单芯片显示应用中的亮度。 SCR概念要求将多种颜色同时映像到SLM阵列上。 这要求将SLM分为复位组，以便单独的像素组可以同时投影来自不同颜色的位。 随着这些色带602,604,606在阵列上滚动，各种复位组跟踪这些区域并改变内容以匹配。 该方法要求将设备划分和控制在独立的复位组级别，每个组被延迟来自先前组的组 - 时间608。 这种方法确保所有颜色都同时在SLM上完成，使颜色混合始终保持一致，以确保良好的色彩强度。 最后，称为辐条1010的颜色带之间的过渡时间期间的光被加在一起作为进一步增加系统亮度的白光。

公开(公告)号：US06573951B1

公开(公告)日：2003-06-03

申请号：US09413582

申请日：1999-10-06

Applicant: Gregory J. Hewlett ,  Donald B. Doherty

Inventor： Gregory J. Hewlett ,  Donald B. Doherty

IPC: H04N574

CPC classification number: H04N9/3123 ,  H04N5/7458 ,  H04N9/3114

Abstract: A method for using pulse-width modulation in displays. A series of PWM sequences is established. Each subsequent sequence clears the previous sequence before it, eliminating the need for a separate clearing reset at the end of the previous sequence. This allows for use of spoke bits in color-sequential systems. In non-color sequential systems and rapid color-switching systems it allows the sequence for one frame to flow directly into the sequence for the next frame.

Abstract translation: 一种在显示器中使用脉宽调制的方法。 建立了一系列PWM序列。 每个后续序列清除之前的前一个序列，从而无需在上一个序列结束时进行单独的清除重置。 这允许在颜色顺序系统中使用辐条位。 在非色顺序系统和快速颜色切换系统中，它允许一帧的序列直接流入下一帧的序列。

公开(公告)号：US06480177B2

公开(公告)日：2002-11-12

申请号：US09088673

申请日：1998-06-02

Applicant: Donald B. Doherty ,  Henry Chu ,  James D. Huffman

Inventor： Donald B. Doherty ,  Henry Chu ,  James D. Huffman

IPC: G09G334

CPC classification number: G09G3/346 ,  G09G2310/062

Abstract: A method of addressing an array of spatial light modulator elements. The method divides the array into blocks of elements, provides reset lines (MRST) to each of the block of elements, separate from the other blocks of elements, as well as address voltage supplies (VCCADDR) to each of the block of elements, separate from the other blocks of elements, addresses data to each of the blocks independent of the other blocks, resets each of the blocks, and steps address voltage to each of the block, where only blocks that are being reset receive the stepped address voltage. A spatial light modulator array (32) is also provided that has a layout to facilitate the method, including internal or external circuitry (34) to provide control of the stepped addressing voltages.

Abstract translation: 寻址空间光调制器元件阵列的方法。 该方法将阵列分成多个元素块，为每个元素块提供复位线（MRST），与元素的其他块分离，以及每个元素块的地址电压供应（VCCADDR），分别 从其他块的块中，独立于其他块的块中的每个块地址数据，复位每个块，并且对每个块执行地址电压，其中只有正在复位的块接收阶梯式地址电压。 还提供了空间光调制器阵列（32），其具有便于该方法的布局，包括内部或外部电路（34）以提供对阶梯式寻址电压的控制。

公开(公告)号：US5528317A

公开(公告)日：1996-06-18

申请号：US188266

申请日：1994-01-27

Applicant: Robert J. Gove ,  Donald B. Doherty

Inventor： Robert J. Gove ,  Donald B. Doherty

IPC: H04N9/30 ,  H04N9/12

CPC classification number: H04N9/30

Abstract: A method and apparatus for synchronizing display timing in a digital television system with a pixel addressable display having a color wheel is disclosed. The display timing circuit 22 includes phase comparator 40, for comparing the phase of a wheel index signal generated by a color wheel 20 with the phase of a frame synchronization signal indicating that a complete frame is ready to be displayed. Display timing circuit 22 further comprises a color wheel synchronization generator 42 which generates a color wheel synchronization signal in response to a phase difference value produced by phase comparator 40. The color wheel synchronization signal is used to increase, decrease, or maintain the speed of color wheel 20 to achieve a known phase relationship between the frame synchronization signal and the wheel index signal. Display timing circuit 22 further comprises a clock generator applicable to generate a display master clock signal having a known frequency relation to the wheel index signal.

Abstract translation: 公开了一种用于将数字电视系统中的显示定时与具有色轮的像素可寻址显示器同步的方法和装置。 显示定时电路22包括相位比较器40，用于将由色轮20产生的车轮指标信号的相位与指示完整帧准备显示的帧同步信号的相位进行比较。 显示定时电路22还包括色轮同步发生器42，其根据由相位比较器40产生的相位差产生色轮同步信号。色轮同步信号用于增加，降低或维持颜色速度 以实现帧同步信号和车轮索引信号之间已知的相位关系。 显示定时电路22还包括时钟发生器，其适用于产生与车轮指标信号具有已知频率关系的显示主时钟信号。

公开(公告)号：US5497197A

公开(公告)日：1996-03-05

申请号：US147801

申请日：1993-11-04

Applicant: Robert J. Gove ,  Donald B. Doherty ,  Stephen W. Marshall ,  Carl W. Davis ,  Joseph G. Egan ,  Richard C. Meyer ,  Jeffrey B. Sampsell ,  Scott D. Heimbuch

Inventor： Robert J. Gove ,  Donald B. Doherty ,  Stephen W. Marshall ,  Carl W. Davis ,  Joseph G. Egan ,  Richard C. Meyer ,  Jeffrey B. Sampsell ,  Scott D. Heimbuch

IPC: H04N5/922 ,  H04N5/14 ,  H04N5/44 ,  H04N5/74 ,  H04N5/937 ,  H04N7/26 ,  H04N7/30 ,  H04N7/50 ,  H04N11/04 ,  H04N7/12 ,  H04N11/02

CPC classification number: H04N5/14 ,  H04N19/436 ,  H04N19/61 ,  H04N5/7458 ,  H04N9/3147 ,  H04N19/30 ,  H04N2005/7466 ,  H04N7/0122

Abstract: A system (30) for packing data into a video processor is provided. System (30) comprises demultiplexer (32), first and second first in-first out buffer memories (34) and (36), and multiplexer (38). Demultiplexer (32) divides a field of video data into first and second parts (42) and (44). First and second parts (42) and (44) are stored in first first in-first out buffer memories (34) and (36), respectively. Multiplexer (38) combines one line from first first in-first out buffer memory (34) with one line from second first in-first out buffer memory (36) to form a single line for processing.

Abstract translation: 提供了一种用于将数据打包到视频处理器中的系统（30）。 系统（30）包括解复用器（32），第一和第二先进先出缓冲存储器（34）和（36）以及多路复用器（38）。 解复用器（32）将视频数据的区域划分为第一和第二部分（42）和（44）。 第一和第二部分（42）和（44）分别存储在第一先进先出缓冲存储器（34）和（36）中。 多路复用器（38）将来自第一先进先出缓冲存储器（34）的一行与来自第二先进先出缓冲存储器（36）的一行组合以形成一行用于处理。

公开(公告)号：US5365283A

公开(公告)日：1994-11-15

申请号：US93537

申请日：1993-07-19

Applicant: Donald B. Doherty ,  Richard C. Meyer ,  Stephen W. Marshall ,  Jeffrey B. Sampsell ,  Robert J. Gove

Inventor： Donald B. Doherty ,  Richard C. Meyer ,  Stephen W. Marshall ,  Jeffrey B. Sampsell ,  Robert J. Gove

IPC: H04N9/31 ,  H04N9/14 ,  H04N9/47

CPC classification number: H04N9/3179 ,  H04N9/3114 ,  G09G2310/0235

Abstract: A SLM-based projection display system (10) samples and processes video data for delivery to a spatial light modulator (SLM) (13c), and uses a color wheel (14a) to color the SLM-generated images. A frame memory (13b) provides data to the SLM (13c) and is managed so that, if the phase of the incoming video signal changes, a desired phase relationship between the color wheel position and the data available to the SLM (13c) can be maintained. Also, a motor control unit (15a) uses a horizontal sync signal to generate a drive signal for the color wheel motor (16a), which limits the transient time during phase-changing events, and which provides a means for adjusting the phase of the drive signal.

Abstract translation: 基于SLM的投影显示系统（10）对用于传送到空间光调制器（SLM）（13c）的视频数据进行采样和处理，并使用色轮（14a）对SLM生成的图像进行着色。 帧存储器（13b）向SLM（13c）提供数据并被管理，使得如果输入视频信号的相位改变，则色轮位置和可用于SLM（13c）的数据之间的期望的相位关系可以 保持。 此外，电动机控制单元（15a）使用水平同步信号来生成用于色轮电动机（16a）的驱动信号，这限制了相变事件期间的瞬时时间，并且其提供了用于调整 驱动信号。

公开(公告)号：US08040305B2

公开(公告)日：2011-10-18

申请号：US11394484

申请日：2006-03-31

Applicant: Daniel J. Morgan ,  Donald B. Doherty ,  William J. Sexton

Inventor： Daniel J. Morgan ,  Donald B. Doherty ,  William J. Sexton

IPC: G09G3/34

CPC classification number: H04N9/3117 ,  G09G3/2014 ,  G09G3/34 ,  G09G5/02 ,  G09G2310/0235

Abstract: A display system 100 includes a light source 110 and a color wheel 114. An optical section 112 is arranged to receive light from the light source 110 and to direct the light toward a color wheel 114. A digital micromirror device 122 is arranged to receive the light from the color wheel 114 and to direct image data toward a display. The image data includes an array of pixels arranged in rows and columns. The array of pixels is arranged as curved color bands during a first time period and rectangular color bands during a second time period. The second time period being concurrent with but of a shorter duration than the first time period.

Abstract translation: 显示系统100包括光源110和色轮114.光学部分112布置成接收来自光源110的光并将光引向色轮114.数字微镜装置122被布置成接收 来自色轮114的光并且将图像数据引导到显示器。 图像数据包括以行和列排列的像素阵列。 像素阵列在第一时间期间被布置为弯曲的色带，并且在第二时间期间被布置成矩形的彩色带。 第二时间段与第一时间段同时但持续时间较短。

公开(公告)号：US07876298B2

公开(公告)日：2011-01-25

申请号：US11257268

申请日：2005-10-24

Applicant: Gregory J. Hewlett ,  Donald B. Doherty

Inventor： Gregory J. Hewlett ,  Donald B. Doherty

IPC: G09G3/34

CPC classification number: G09G3/346 ,  G02B26/0841 ,  G09G3/2037 ,  H04N5/7458 ,  H04N9/3102 ,  H04N9/3114 ,  H04N9/312

Abstract: A spatial light modulator clocking method, called fast-clear, which employs embedded clear hardware in the SLM to enable the fast-clear bit to generate least-significant short-bit periods and without any bit ordering restrictions. In this method, fast data clears 34 are inserted between block data loads 32,36 within a frame refresh period. This method virtually eliminates the artifacts associated with the earlier reset-release timing method without the bit-ordering restriction of the jog-clear method.

Abstract translation: 一种称为快清晰度的空间光调制器时钟方法，其在SLM中采用嵌入式清晰硬件，以使快速清除位产生最低有效的短位周期，并且没有任何位排序限制。 在该方法中，在帧刷新周期内的块数据加载32,36之间插入快速数据清除34。 该方法实际上消除了与较早的复位释放定时方法相关联的伪像，而没有点动清除方法的位排序限制。

公开(公告)号：US20080151195A1

公开(公告)日：2008-06-26

申请号：US11614105

申请日：2006-12-21

Applicant: Roman J. Pacheco ,  Donald B. Doherty ,  Larry D. Dickinson

Inventor： Roman J. Pacheco ,  Donald B. Doherty ,  Larry D. Dickinson

IPC: G03B21/26

CPC classification number: G03B21/26

Abstract: An apparatus for, and method of, increasing compensation sequence storage density in a projection visual display system and a projection visual display system incorporating the apparatus or the method. In one embodiment, the apparatus includes: (1) a memory containing a first compensation sequence portion that is common to a plurality of effective transmission factors and a plurality of second compensation sequence portions that are unique to a corresponding plurality of effective transmission factors and (2) a compensation sequence generator coupled to the memory and configured to construct a compensation sequence for use in the projection visual display system using the first compensation sequence portion and one of the plurality of second compensation sequence portions selected as a function of a particular effective transmission factor.

Abstract translation: 一种用于增加投影视觉显示系统中的补偿顺序存储密度的装置和方法，以及包含该装置或方法的投影视觉显示系统。 在一个实施例中，该装置包括：（1）存储器，其包含多个有效传输因子共有的第一补偿序列部分和对应的多个有效传输因子是唯一的多个第二补偿序列部分，和 2）补偿序列发生器，其耦合到所述存储器并且被配置为构建使用所述投影视觉显示系统中的补偿序列，所述补偿序列部分使用所述第一补偿序列部分和作为特定有效传输的函数选择的所述多个第二补偿序列部分中的一个 因子。