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公开(公告)号：US20120106257A1
公开(公告)日：2012-05-03
申请号：US13346880
申请日：2012-01-10
CPC分类号： G11C16/14 , G11C16/16 , G11C16/3445
摘要： For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.
摘要翻译： 对于从电可擦除和可编程的非易失性存储单元进行的数据擦除，执行以下操作：将擦除脉冲电压施加到用于数据擦除的存储单元的擦除操作，擦除验证操作以验证数据擦除是否完成， 以及如果数据擦除未完成，则通过一定的升压电压来增加擦除脉冲电压的升压操作。 控制单元控制电压，使得在擦除操作中最初产生的至少第一擦除脉冲电压具有比在第一擦除脉冲电压之后产生的第二擦除脉冲电压更长的上升时间。
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公开(公告)号：US20110228608A1
公开(公告)日：2011-09-22
申请号：US12885066
申请日：2010-09-17
申请人： Yasuhiro Shiino , Eietsu Takahashi
发明人： Yasuhiro Shiino , Eietsu Takahashi
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483
摘要： According to one embodiment, a nonvolatile semiconductor memory device comprises a first memory cell, a second memory cell, and a control circuit. The first memory cell is connected to a first word line. The second memory cell is connected to a second word line which is adjacent to the first word line and has a width different from a width of the first word line. The control circuit applies a first voltage to the first word line and a second voltage different from the first voltage to the second word line. At least one of the first voltage and the second voltage is corrected by the control circuit based on write loop counts of the first memory cell and the second memory cell when the first memory cell and the second memory cell are write target cells in a write operation.
摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一存储单元，第二存储单元和控制电路。 第一存储单元连接到第一字线。 第二存储单元连接到与第一字线相邻的第二字线，并且具有与第一字线的宽度不同的宽度。 控制电路将第一电压施加到第一字线，并将第一电压与第一电压不同于第二字线。 当第一存储单元和第二存储单元在写入操作中写入目标单元时，基于第一存储单元和第二存储器单元的写入循环计数，控制电路校正第一电压和第二电压中的至少一个电压 。
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公开(公告)号：US08976597B2
公开(公告)日：2015-03-10
申请号：US13227050
申请日：2011-09-07
申请人： Yasuhiro Shiino , Eietsu Takahashi , Koki Ueno
发明人： Yasuhiro Shiino , Eietsu Takahashi , Koki Ueno
CPC分类号： G11C16/16 , G11C16/3445 , G11C16/345
摘要： A control circuit executes an erase operation that includes an erase pulse application operation and an erase verify operation. The erase pulse application operation applies an erase pulse voltage to a memory cell to change the memory cell from a write state to an erase state. The erase verify operation applies an erase verify voltage to the memory cell to judge whether the memory cell is in the erase state or not. The control circuit changes conditions of execution of the erase verify operation when the number of times of executions of the erase pulse application operation in one erase operation reaches a first number.
摘要翻译： 控制电路执行包括擦除脉冲施加操作和擦除验证操作的擦除操作。 擦除脉冲施加操作将擦除脉冲电压施加到存储单元，以将存储单元从写入状态改变为擦除状态。 擦除验证操作将擦除验证电压施加到存储器单元以判断存储器单元是否处于擦除状态。 当在一个擦除操作中执行擦除脉冲施加操作的次数达到第一数量时，控制电路改变擦除验证操作的执行条件。
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公开(公告)号：US08605514B2
公开(公告)日：2013-12-10
申请号：US12885066
申请日：2010-09-17
申请人： Yasuhiro Shiino , Eietsu Takahashi
发明人： Yasuhiro Shiino , Eietsu Takahashi
IPC分类号： G11C11/40
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483
摘要： According to one embodiment, a nonvolatile semiconductor memory device comprises a first memory cell, a second memory cell, and a control circuit. The first memory cell is connected to a first word line. The second memory cell is connected to a second word line which is adjacent to the first word line and has a width different from a width of the first word line. The control circuit applies a first voltage to the first word line and a second voltage different from the first voltage to the second word line. At least one of the first voltage and the second voltage is corrected by the control circuit based on write loop counts of the first memory cell and the second memory cell when the first memory cell and the second memory cell are write target cells in a write operation.
摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一存储单元，第二存储单元和控制电路。 第一存储单元连接到第一字线。 第二存储单元连接到与第一字线相邻的第二字线，并且具有与第一字线的宽度不同的宽度。 控制电路将第一电压施加到第一字线，并将第一电压与第一电压不同于第二字线。 当第一存储单元和第二存储单元在写入操作中写入目标单元时，基于第一存储单元和第二存储器单元的写入循环计数，控制电路校正第一电压和第二电压中的至少一个电压 。
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公开(公告)号：US08599617B2
公开(公告)日：2013-12-03
申请号：US13457560
申请日：2012-04-27
申请人： Yasuhiro Shiino , Eietsu Takahashi
发明人： Yasuhiro Shiino , Eietsu Takahashi
CPC分类号： G11C16/0483 , G11C11/5635 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/28 , G11C16/3404 , G11C16/3413 , G11C16/344 , G11C16/3445 , G11C16/3463 , G11C2211/5621
摘要： A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
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公开(公告)号：US08422301B2
公开(公告)日：2013-04-16
申请号：US13169414
申请日：2011-06-27
申请人： Yasuhiro Shiino , Eietsu Takahashi , Yuji Takeuchi
发明人： Yasuhiro Shiino , Eietsu Takahashi , Yuji Takeuchi
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3418
摘要： A nonvolatile semiconductor memory device in accordance with an embodiment includes a memory cell array. A control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write operation being an operation to apply a write pulse voltage to a selected memory cell and an intermediate voltage to an unselected memory cell. The control unit controls the step-up operation such that, in a first period, the intermediate voltage is maintained at a constant value, and, in a second period, the intermediate voltage is raised by a certain value. The control unit controls the step-up operation such that the first period includes an operation to raise the write pulse voltage by a first step-up value, and the second period includes an operation to raise the write pulse voltage by a second step-up value smaller than the first step-up value.
摘要翻译： 根据实施例的非易失性半导体存储器件包括存储单元阵列。 控制单元执行重复写入操作，写入验证操作和升压操作的控制，写入操作是将写入脉冲电压施加到所选择的存储器单元和中间电压到未选择存储单元的操作。 控制单元控制升压操作，使得在第一时间段中，中间电压保持在恒定值，并且在第二时间段内将中间电压升高一定值。 控制单元控制升压操作，使得第一周期包括用于将写入脉冲电压升高第一升压值的操作，并且第二周期包括通过第二升压升高写入脉冲电压的操作 值小于第一升压值。
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公开(公告)号：US20120281487A1
公开(公告)日：2012-11-08
申请号：US13288485
申请日：2011-11-03
IPC分类号： G11C7/22
CPC分类号： G11C16/10 , G11C16/0483
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array includes a plurality of memory cell units which are arranged at intersections of a plurality of bit lines and a plurality of word lines and whose current paths are connected in series, a voltage generator circuit which generates a voltage to be applied to the memory cell array, and a control circuit which controls the memory cell array and the voltage generator circuit. The control circuit, when writing data into the memory cell array, performs control so as to apply a first write pass voltage to unselected word lines in the memory cell units and, after a selected word line has reached a write voltage, further apply a voltage to the unselected word lines until a second write pass voltage higher than the first write pass voltage has been reached.
摘要翻译： 根据一个实施例，一种半导体存储器件包括：存储单元阵列，包括布置在多个位线和多个字线的交点处并且其电流通路串联连接的多个存储单元单元;电压发生器 产生施加到存储单元阵列的电压的电路，以及控制存储单元阵列和电压发生器电路的控制电路。 控制电路在将数据写入存储单元阵列时进行控制，以对存储单元单元中的未选字线施加第一写入通过电压，并且在所选字线达到写入电压之后，进一步施加电压 到未选择的字线，直到达到高于第一写入通过电压的第二写入通过电压。
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公开(公告)号：US20120206968A1
公开(公告)日：2012-08-16
申请号：US13457560
申请日：2012-04-27
申请人： Yasuhiro Shiino , Eietsu Takahashi
发明人： Yasuhiro Shiino , Eietsu Takahashi
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5635 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/28 , G11C16/3404 , G11C16/3413 , G11C16/344 , G11C16/3445 , G11C16/3463 , G11C2211/5621
摘要： A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
摘要翻译： 非易失性半导体存储器件包括：控制电路，被配置为控制将非易失性存储器单元设置为非易失性存储单元的第一阈值电压分布状态的软编程操作。 当非易失性存储单元的特性处于第一状态时，控制电路通过将用于将非易失性存储单元设置为第一阈值电压分布状态的第一电压施加到第一字线来执行软编程操作，并且施加第二电压 高于第一个电压到第二个字线。 当非易失性存储单元的特性处于第二状态时，控制电路通过向第一字线施加等于或低于第一电压的第三电压并施加低于第二电压的第四电压来执行软编程操作 到第二个字线。
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公开(公告)号：US20120072648A1
公开(公告)日：2012-03-22
申请号：US13226826
申请日：2011-09-07
IPC分类号： G06F12/02
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3459
摘要： A nonvolatile semiconductor memory device in accordance with an embodiment includes: a memory cell array having electrically rewritable nonvolatile memory cells; and a control unit. The control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write verify operation being an operation to verify whether data write is completed or not, and the step-up operation being an operation to raise the write pulse voltage if data write is not completed. The control unit, during the write operation, raises a first write pulse voltage with a first gradient, and then raises a second write pulse voltage with a second gradient, thereby executing the write operation, the first write pulse voltage including at least a write pulse voltage generated at first, the second write pulse voltage being generated after the first write pulse voltage, and the second gradient being larger than the first gradient.
摘要翻译： 根据实施例的非易失性半导体存储器件包括：具有电可重写非易失性存储单元的存储单元阵列; 和控制单元。 控制单元执行重复写入操作，写入验证操作和升压操作的控制，写入验证操作是用于验证数据写入是否完成的操作，并且升压操作是对 如果数据写入未完成，则提高写脉冲电压。 控制单元在写入操作期间，以第一梯度升高第一写入脉冲电压，然后以第二梯度提升第二写入脉冲电压，由此执行写入操作，第一写入脉冲电压至少包括写入脉冲 首先产生电压，第二写脉冲电压在第一写入脉冲电压之后产生，第二梯度大于第一梯度。
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公开(公告)号：US20110063917A1
公开(公告)日：2011-03-17
申请号：US12878624
申请日：2010-09-09
申请人： Yasuhiro Shiino , Eietsu Takahashi
发明人： Yasuhiro Shiino , Eietsu Takahashi
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5635 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/28 , G11C16/3404 , G11C16/3413 , G11C16/344 , G11C16/3445 , G11C16/3463 , G11C2211/5621
摘要： A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
摘要翻译： 非易失性半导体存储器件包括：控制电路，被配置为控制将非易失性存储器单元设置为非易失性存储单元的第一阈值电压分布状态的软编程操作。 当非易失性存储单元的特性处于第一状态时，控制电路通过将用于将非易失性存储单元设置为第一阈值电压分布状态的第一电压施加到第一字线来执行软编程操作，并且施加第二电压 高于第一个电压到第二个字线。 当非易失性存储单元的特性处于第二状态时，控制电路通过向第一字线施加等于或低于第一电压的第三电压并施加低于第二电压的第四电压来执行软编程操作 到第二个字线。
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