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1.发明申请SEMICONDUCTOR STORAGE DEVICE ADAPTED TO PREVENT ERRONEOUS WRITING TO NON-SELECTED MEMORY CELLS 有权半导体存储器件适合于防止错误地写入非选择的存储器单元公开(公告)号：US20120147670A1
公开(公告)日：2012-06-14
申请号：US13400930
申请日：2012-02-21
申请人： Noboru SHIBATA , Kenri Nakai
发明人： Noboru SHIBATA , Kenri Nakai
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5642
摘要： A memory cell array has a number of memory cells which are connected to word lines and bit lines and are arranged in a matrix form, each of the memory cells storing one of n levels (n is a natural number of 2 or more). A control circuit controls the potentials on the word lines and the bit lines in accordance with input data to write data to the memory cells. The control circuit is adapted to, at the write time, first apply a first potential to a well region or substrate in which the memory cells are formed, then set the well region or substrate to a second potential lower than the first potential, and next apply a predetermined voltage to the word lines to thereby perform a write operation.
摘要翻译： 存储单元阵列具有连接到字线和位线并且以矩阵形式布置的多个存储单元，每个存储单元存储n个电平中的一个（n是2或更多的自然数）。 控制电路根据输入数据控制字线和位线上的电位，以将数据写入存储单元。 控制电路适于在写入时刻首先将第一电位施加到其中形成存储器单元的阱区或衬底，然后将阱区或衬底设置为低于第一电位的第二电位，接下来 对字线施加预定的电压从而执行写入操作。
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2.发明授权Semiconductor storage device adapted to prevent erroneous writing to non-selected memory cells 有权半导体存储装置适于防止对未选择的存储单元的错误写入公开(公告)号：US08416629B2
公开(公告)日：2013-04-09
申请号：US13400930
申请日：2012-02-21
申请人： Noboru Shibata , Kenri Nakai
发明人： Noboru Shibata , Kenri Nakai
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5642
摘要： A memory cell array has a number of memory cells which are connected to word lines and bit lines and are arranged in a matrix form, each of the memory cells storing one of n levels (n is a natural number of 2 or more). A control circuit controls the potentials on the word lines and the bit lines in accordance with input data to write data to the memory cells. The control circuit is adapted to, at the write time, first apply a first potential to a well region or substrate in which the memory cells are formed, then set the well region or substrate to a second potential lower than the first potential, and next apply a predetermined voltage to the word lines to thereby perform a write operation.
摘要翻译： 存储单元阵列具有连接到字线和位线并且以矩阵形式布置的多个存储单元，每个存储单元存储n个电平中的一个（n是2或更多的自然数）。 控制电路根据输入数据控制字线和位线上的电位，以将数据写入存储单元。 控制电路适于在写入时刻首先将第一电位施加到其中形成存储器单元的阱区或衬底，然后将阱区或衬底设置为低于第一电位的第二电位，接下来 对字线施加预定的电压从而执行写入操作。
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公开(公告)号：US20120072648A1
公开(公告)日：2012-03-22
申请号：US13226826
申请日：2011-09-07
IPC分类号： G06F12/02
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3459
摘要： A nonvolatile semiconductor memory device in accordance with an embodiment includes: a memory cell array having electrically rewritable nonvolatile memory cells; and a control unit. The control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write verify operation being an operation to verify whether data write is completed or not, and the step-up operation being an operation to raise the write pulse voltage if data write is not completed. The control unit, during the write operation, raises a first write pulse voltage with a first gradient, and then raises a second write pulse voltage with a second gradient, thereby executing the write operation, the first write pulse voltage including at least a write pulse voltage generated at first, the second write pulse voltage being generated after the first write pulse voltage, and the second gradient being larger than the first gradient.
摘要翻译： 根据实施例的非易失性半导体存储器件包括：具有电可重写非易失性存储单元的存储单元阵列; 和控制单元。 控制单元执行重复写入操作，写入验证操作和升压操作的控制，写入验证操作是用于验证数据写入是否完成的操作，并且升压操作是对 如果数据写入未完成，则提高写脉冲电压。 控制单元在写入操作期间，以第一梯度升高第一写入脉冲电压，然后以第二梯度提升第二写入脉冲电压，由此执行写入操作，第一写入脉冲电压至少包括写入脉冲 首先产生电压，第二写脉冲电压在第一写入脉冲电压之后产生，第二梯度大于第一梯度。
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公开(公告)号：US20110013461A1
公开(公告)日：2011-01-20
申请号：US12796964
申请日：2010-06-09
CPC分类号： G11C16/14 , G11C16/16 , G11C16/3445
摘要： For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.
摘要翻译： 对于从电可擦除和可编程的非易失性存储单元进行的数据擦除，执行以下操作：将擦除脉冲电压施加到用于数据擦除的存储单元的擦除操作，擦除验证操作以验证数据擦除是否完成， 以及如果数据擦除未完成，则通过一定的升压电压来增加擦除脉冲电压的升压操作。 控制单元控制电压，使得在擦除操作中最初产生的至少第一擦除脉冲电压具有比在第一擦除脉冲电压之后产生的第二擦除脉冲电压更长的上升时间。
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公开(公告)号：US20130058171A1
公开(公告)日：2013-03-07
申请号：US13425121
申请日：2012-03-20
申请人： Yasuhiro SHIINO , Shigefumi Irieda , Kenri Nakai , Eietsu Takahashi , Koki Ueno
发明人： Yasuhiro SHIINO , Shigefumi Irieda , Kenri Nakai , Eietsu Takahashi , Koki Ueno
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/3418
摘要： A semiconductor storage device has a plurality of memory cells each having a control gate that are formed on a well. The semiconductor storage device has a control circuit that applies a voltage to the well and the control gates.In an erase operation of the memory cell, the control circuit applies a first pulse wave of a first erasure voltage that rises stepwise to the well and then applies a second pulse wave of a second erasure voltage to the well.
摘要翻译： 半导体存储装置具有多个存储单元，每个存储单元具有形成在阱上的控制栅极。 半导体存储装置具有向井和控制门施加电压的控制电路。 在存储单元的擦除操作中，控制电路施加第一擦除电压的第一脉冲波，该第一脉冲波逐步上升到阱，然后向阱施加第二擦除电压的第二脉冲波。
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公开(公告)号：US08149631B2
公开(公告)日：2012-04-03
申请号：US12796964
申请日：2010-06-09
IPC分类号： G11C11/34
CPC分类号： G11C16/14 , G11C16/16 , G11C16/3445
摘要： For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.
摘要翻译： 对于从电可擦除和可编程的非易失性存储单元进行的数据擦除，执行以下操作：将擦除脉冲电压施加到用于数据擦除的存储单元的擦除操作，擦除验证操作以验证数据擦除是否完成， 以及如果数据擦除未完成，则通过一定的升压电压来增加擦除脉冲电压的升压操作。 控制单元控制电压，使得在擦除操作中最初产生的至少第一擦除脉冲电压具有比在第一擦除脉冲电压之后产生的第二擦除脉冲电压更长的上升时间。
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公开(公告)号：US08953371B2
公开(公告)日：2015-02-10
申请号：US13425121
申请日：2012-03-20
申请人： Yasuhiro Shiino , Shigefumi Irieda , Kenri Nakai , Eietsu Takahashi , Koki Ueno
发明人： Yasuhiro Shiino , Shigefumi Irieda , Kenri Nakai , Eietsu Takahashi , Koki Ueno
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/3418
摘要： A semiconductor storage device has a plurality of memory cells each having a control gate that are formed on a well. The semiconductor storage device has a control circuit that applies a voltage to the well and the control gates.In an erase operation of the memory cell, the control circuit applies a first pulse wave of a first erasure voltage that rises stepwise to the well and then applies a second pulse wave of a second erasure voltage to the well.
摘要翻译： 半导体存储装置具有多个存储单元，每个存储单元具有形成在阱上的控制栅极。 半导体存储装置具有向井和控制门施加电压的控制电路。 在存储单元的擦除操作中，控制电路施加第一擦除电压的第一脉冲波，该第一脉冲波逐步上升到阱，然后向阱施加第二擦除电压的第二脉冲波。
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公开(公告)号：US08531891B2
公开(公告)日：2013-09-10
申请号：US13346880
申请日：2012-01-10
IPC分类号： G11C11/34
CPC分类号： G11C16/14 , G11C16/16 , G11C16/3445
摘要： For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.
摘要翻译： 对于从电可擦除和可编程的非易失性存储单元进行的数据擦除，执行以下操作：将擦除脉冲电压施加到用于数据擦除的存储单元的擦除操作，擦除验证操作以验证数据擦除是否完成， 以及如果数据擦除未完成，则通过一定的升压电压来增加擦除脉冲电压的升压操作。 控制单元控制电压，使得在擦除操作中最初产生的至少第一擦除脉冲电压具有比在第一擦除脉冲电压之后产生的第二擦除脉冲电压更长的上升时间。
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9.发明授权Nonvolatile semiconductor memory device using write pulses with different voltage gradients 有权非易失性半导体存储器件使用具有不同电压梯度的写入脉冲公开(公告)号：US08848447B2
公开(公告)日：2014-09-30
申请号：US13226826
申请日：2011-09-07
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3459
摘要： A nonvolatile semiconductor memory device in accordance with an embodiment includes: a memory cell array having electrically rewritable nonvolatile memory cells; and a control unit. The control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write verify operation being an operation to verify whether data write is completed or not, and the step-up operation being an operation to raise the write pulse voltage if data write is not completed. The control unit, during the write operation, raises a first write pulse voltage with a first gradient, and then raises a second write pulse voltage with a second gradient, thereby executing the write operation, the first write pulse voltage including at least a write pulse voltage generated at first, the second write pulse voltage being generated after the first write pulse voltage, and the second gradient being larger than the first gradient.
摘要翻译： 根据实施例的非易失性半导体存储器件包括：具有电可重写非易失性存储单元的存储单元阵列; 和控制单元。 控制单元执行重复写入操作，写入验证操作和升压操作的控制，写入验证操作是用于验证数据写入是否完成的操作，并且升压操作是对 如果数据写入未完成，则提高写脉冲电压。 控制单元在写入操作期间，以第一梯度升高第一写入脉冲电压，然后以第二梯度提升第二写入脉冲电压，由此执行写入操作，第一写入脉冲电压至少包括写入脉冲 首先产生电压，第二写脉冲电压在第一写入脉冲电压之后产生，第二梯度大于第一梯度。
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公开(公告)号：US20120106257A1
公开(公告)日：2012-05-03
申请号：US13346880
申请日：2012-01-10
CPC分类号： G11C16/14 , G11C16/16 , G11C16/3445
摘要： For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.
摘要翻译： 对于从电可擦除和可编程的非易失性存储单元进行的数据擦除，执行以下操作：将擦除脉冲电压施加到用于数据擦除的存储单元的擦除操作，擦除验证操作以验证数据擦除是否完成， 以及如果数据擦除未完成，则通过一定的升压电压来增加擦除脉冲电压的升压操作。 控制单元控制电压，使得在擦除操作中最初产生的至少第一擦除脉冲电压具有比在第一擦除脉冲电压之后产生的第二擦除脉冲电压更长的上升时间。
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