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公开(公告)号：US08446777B2
公开(公告)日：2013-05-21
申请号：US13280618
申请日：2011-10-25
CPC分类号： G11C16/14 , G11C11/5635 , G11C16/16 , G11C16/344
摘要： A non-volatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array and a control unit. The control unit is configured to control a repeat of an erase operation, an erase verify operation, and a step-up operation. The control unit is configured to perform a soft-programming operation of setting the memory cells from an over-erased state to a first threshold voltage distribution state when, in a series of erase operations, the number of erase voltage applications is more than a first number and less than a second number (the first number
摘要翻译： 根据本发明的一个实施例的非易失性半导体存储器件包括存储单元阵列和控制单元。 控制单元被配置为控制擦除操作，擦除验证操作和升压操作的重复。 控制单元被配置为执行将存储单元从过擦除状态设置为第一阈值电压分布状态的软编程操作，当在一系列擦除操作中擦除电压应用的数量多于第一阈值电压分配状态时， 数字和小于第二个数字（第一个数字<第二个数字）。 当擦除电压应用的数量等于或小于第一数量或等于或大于第二数量时，控制单元被配置为不执行软编程操作。
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公开(公告)号：US20130058171A1
公开(公告)日：2013-03-07
申请号：US13425121
申请日：2012-03-20
申请人： Yasuhiro SHIINO , Shigefumi Irieda , Kenri Nakai , Eietsu Takahashi , Koki Ueno
发明人： Yasuhiro SHIINO , Shigefumi Irieda , Kenri Nakai , Eietsu Takahashi , Koki Ueno
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/3418
摘要： A semiconductor storage device has a plurality of memory cells each having a control gate that are formed on a well. The semiconductor storage device has a control circuit that applies a voltage to the well and the control gates.In an erase operation of the memory cell, the control circuit applies a first pulse wave of a first erasure voltage that rises stepwise to the well and then applies a second pulse wave of a second erasure voltage to the well.
摘要翻译： 半导体存储装置具有多个存储单元，每个存储单元具有形成在阱上的控制栅极。 半导体存储装置具有向井和控制门施加电压的控制电路。 在存储单元的擦除操作中，控制电路施加第一擦除电压的第一脉冲波，该第一脉冲波逐步上升到阱，然后向阱施加第二擦除电压的第二脉冲波。
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公开(公告)号：US08149631B2
公开(公告)日：2012-04-03
申请号：US12796964
申请日：2010-06-09
IPC分类号： G11C11/34
CPC分类号： G11C16/14 , G11C16/16 , G11C16/3445
摘要： For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.
摘要翻译： 对于从电可擦除和可编程的非易失性存储单元进行的数据擦除，执行以下操作：将擦除脉冲电压施加到用于数据擦除的存储单元的擦除操作，擦除验证操作以验证数据擦除是否完成， 以及如果数据擦除未完成，则通过一定的升压电压来增加擦除脉冲电压的升压操作。 控制单元控制电压，使得在擦除操作中最初产生的至少第一擦除脉冲电压具有比在第一擦除脉冲电压之后产生的第二擦除脉冲电压更长的上升时间。
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公开(公告)号：US20120069672A1
公开(公告)日：2012-03-22
申请号：US13169414
申请日：2011-06-27
申请人： Yasuhiro SHIINO , Eietsu Takahashi , Yuji Takeuchi
发明人： Yasuhiro SHIINO , Eietsu Takahashi , Yuji Takeuchi
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3418
摘要： A nonvolatile semiconductor memory device in accordance with an embodiment includes a memory cell array. A control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write operation being an operation to apply a write pulse voltage to a selected memory cell and an intermediate voltage to an unselected memory cell. The control unit controls the step-up operation such that, in a first period, the intermediate voltage is maintained at a constant value, and, in a second period, the intermediate voltage is raised by a certain value. The control unit controls the step-up operation such that the first period includes an operation to raise the write pulse voltage by a first step-up value, and the second period includes an operation to raise the write pulse voltage by a second step-up value smaller than the first step-up value.
摘要翻译： 根据实施例的非易失性半导体存储器件包括存储单元阵列。 控制单元执行重复写入操作，写入验证操作和升压操作的控制，写入操作是将写入脉冲电压施加到所选择的存储器单元和中间电压到未选择存储单元的操作。 控制单元控制升压操作，使得在第一时间段中，中间电压保持在恒定值，并且在第二时间段内将中间电压升高一定值。 控制单元控制升压操作，使得第一周期包括用于将写入脉冲电压升高第一升压值的操作，并且第二周期包括通过第二升压升高写入脉冲电压的操作 值小于第一升压值。
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公开(公告)号：US07977733B2
公开(公告)日：2011-07-12
申请号：US12394929
申请日：2009-02-27
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.
摘要翻译： 非易失性半导体存储装置包括：形成有多个电可重写存储单元的存储单元区域; 以及外围电路区域，其中形成配置外围电路以控制存储单元的晶体管。 在其中形成存储单元区域：形成为在垂直方向上延伸到半导体衬底的半导体层; 多个导电层，沿着与半导体基板的垂直方向平行的方向延伸并层叠; 以及形成在所述半导体层和所述导电层之间的性质变化层，并且具有根据施加到所述导电层的电压而变化的特性。 外围电路区域中形成有多个虚拟布线层，其形成在与多个导电层中的每一个相同的平面上，并且与导电层电分离。
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公开(公告)号：US20090230450A1
公开(公告)日：2009-09-17
申请号：US12394929
申请日：2009-02-27
IPC分类号： H01L29/788 , H01L21/20
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.
摘要翻译： 非易失性半导体存储装置包括：形成有多个电可重写存储单元的存储单元区域; 以及外围电路区域，其中形成配置外围电路以控制存储单元的晶体管。 在其中形成存储单元区域：形成为在垂直方向上延伸到半导体衬底的半导体层; 多个导电层，沿着与半导体基板的垂直方向平行的方向延伸并层叠; 以及形成在所述半导体层和所述导电层之间的性质变化层，并且具有根据施加到所述导电层的电压而变化的特性。 外围电路区域中形成有多个虚拟布线层，其形成在与多个导电层中的每一个相同的平面上，并且与导电层电分离。
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7.发明授权Nonvolatile semiconductor memory device using write pulses with different voltage gradients 有权非易失性半导体存储器件使用具有不同电压梯度的写入脉冲公开(公告)号：US08848447B2
公开(公告)日：2014-09-30
申请号：US13226826
申请日：2011-09-07
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3459
摘要： A nonvolatile semiconductor memory device in accordance with an embodiment includes: a memory cell array having electrically rewritable nonvolatile memory cells; and a control unit. The control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write verify operation being an operation to verify whether data write is completed or not, and the step-up operation being an operation to raise the write pulse voltage if data write is not completed. The control unit, during the write operation, raises a first write pulse voltage with a first gradient, and then raises a second write pulse voltage with a second gradient, thereby executing the write operation, the first write pulse voltage including at least a write pulse voltage generated at first, the second write pulse voltage being generated after the first write pulse voltage, and the second gradient being larger than the first gradient.
摘要翻译： 根据实施例的非易失性半导体存储器件包括：具有电可重写非易失性存储单元的存储单元阵列; 和控制单元。 控制单元执行重复写入操作，写入验证操作和升压操作的控制，写入验证操作是用于验证数据写入是否完成的操作，并且升压操作是对 如果数据写入未完成，则提高写脉冲电压。 控制单元在写入操作期间，以第一梯度升高第一写入脉冲电压，然后以第二梯度提升第二写入脉冲电压，由此执行写入操作，第一写入脉冲电压至少包括写入脉冲 首先产生电压，第二写脉冲电压在第一写入脉冲电压之后产生，第二梯度大于第一梯度。
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公开(公告)号：US20130148430A1
公开(公告)日：2013-06-13
申请号：US13707851
申请日：2012-12-07
申请人： Yasuhiro SHIINO , Shigefumi Irieda , Shigeo Kondo
发明人： Yasuhiro SHIINO , Shigefumi Irieda , Shigeo Kondo
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3427 , G11C16/3459
摘要： A non-volatile semiconductor memory device according to one embodiment includes: a cell array; and a data writing unit that repeatedly executes a write loop including a programming operation of applying a program voltage to a selected word line and a passage voltage to non-selected word lines during writing of data, in which, when a difference between the passage voltage used in an n-th write loop and the passage voltage used in an n+1-th write loop is expressed as ΔVn and when a condition of L
摘要翻译： 根据一个实施例的非易失性半导体存储器件包括：单元阵列; 以及数据写入单元，其在写入数据期间重复执行包括对所选字线施加编程电压的编程操作和通过电压到未选择的字线的写入循环，其中当通过电压 用于第n个写入回路，并且在第n + 1写入回路中使用的通过电压被表示为DeltaVn，并且当满足L
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公开(公告)号：US08314455B2
公开(公告)日：2012-11-20
申请号：US13156727
申请日：2011-06-09
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.
摘要翻译： 非易失性半导体存储装置包括：形成有多个电可重写存储单元的存储单元区域; 以及外围电路区域，其中形成配置外围电路以控制存储单元的晶体管。 在其中形成存储单元区域：形成为在垂直方向上延伸到半导体衬底的半导体层; 多个导电层，沿着与半导体基板的垂直方向平行的方向延伸并层叠; 以及形成在所述半导体层和所述导电层之间的性质变化层，并且具有根据施加到所述导电层的电压而变化的特性。 外围电路区域中形成有多个虚拟布线层，其形成在与多个导电层中的每一个相同的平面上，并且与导电层电分离。
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公开(公告)号：US20120281477A1
公开(公告)日：2012-11-08
申请号：US13308736
申请日：2011-12-01
申请人： Manabu Sakaniwa , Koki Ueno , Shigefumi Irieda , Eietsu Takahashi , Yasuhiro Shiino , Daisuke Kouno
发明人： Manabu Sakaniwa , Koki Ueno , Shigefumi Irieda , Eietsu Takahashi , Yasuhiro Shiino , Daisuke Kouno
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/3427
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array includes a plurality of cell units each composed of a plurality of memory cells which are arranged at intersections of a plurality of bit lines and a plurality of word lines and whose current paths are connected in series and select transistors each connected to either end of the series connection, a voltage generator circuit which generates a voltage applied to the memory cell array, and a control circuit which controls the memory cell array and the voltage generator circuit.
摘要翻译： 根据一个实施例，半导体存储器件包括存储单元阵列，其包括多个单元单元，每个单元单元由多个存储单元构成，多个存储单元布置在多个位线和多个字线的交点处，并且其电流路径为 串联连接的晶体管和串联连接的任一端的晶体管，产生施加到存储单元阵列的电压的电压发生器电路以及控制存储单元阵列和电压发生器电路的控制电路。
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