公开(公告)号：US5644761A

公开(公告)日：1997-07-01

申请号：US893871

申请日：1992-06-05

申请人： Ronald W. Yoder ,  Ronald E. Lange ,  William A. Shelly ,  Russell W. Guenthner ,  Richard L. Demers

发明人： Ronald W. Yoder ,  Ronald E. Lange ,  William A. Shelly ,  Russell W. Guenthner ,  Richard L. Demers

IPC分类号： G06F9/26 ,  G06F9/22

CPC分类号： G06F9/267

摘要： In order to efficiently undertake the micro-steps required to execute an extended instruction in a central processing unit, a main sequence controller and a separate basic operations controller having its own sequencer and the ability to run semi-autonomously are provided. Normally, the main sequence controller determines the operation of the basic operations controller, but, in the case of execution of, for example, a multi-word instruction requiring extended basic operations, the basic operations controller temporarily takes control over the main controller until the extended basic operations have been completed. The result is a relatively simple sequencer that supports tight micro-coded functions where many of the sequence decisions can be predetermined.

摘要翻译： 为了有效地执行在中央处理单元中执行扩展指令所需的微步骤，提供了具有其自己的定序器的主序列控制器和单独的基本操作控制器以及半自主运行的能力。 通常，主序列控制器确定基本操作控制器的操作，但是在执行例如需要扩展基本操作的多字指令的情况下，基本操作控制器暂时控制主控制器，直到 扩展基本操作已经完成。 结果是相对简单的定序器，其支持紧密的微编码功能，其中许多顺序决定可以被预先确定。

公开(公告)号：US4594659A

公开(公告)日：1986-06-10

申请号：US434197

申请日：1982-10-13

申请人： Russell W. Guenthner ,  William A. Shelly ,  Gary R. Presley-Nelson ,  Kala J. Marietta ,  R. Morse Wade

发明人： Russell W. Guenthner ,  William A. Shelly ,  Gary R. Presley-Nelson ,  Kala J. Marietta ,  R. Morse Wade

IPC分类号： G06F9/38 ,  G06F9/28

CPC分类号： G06F9/3806 ,  G06F9/322 ,  G06F9/3889

摘要： Method and apparatus for prefetching instructions for a pipelined central processor unit for a general purpose digital data processing system. A table is maintained for purposes of predicting the target addresses of transfer and indirect instructions based on past history of the execution of those instructions. The prefetch mechanism forms instruction addresses and fetches instructions in parallel with the execution of previously fetched instructions by a central execution pipeline unit of the central processor unit. As instructions are prefetched, the transfer and indirect prediction (TIP) table is checked to determine the past history of those instructions. If no transfers or indirects are found, the prefetch proceeds sequentially. If transfer or indirect instructions are found, then the prefetch uses information in the TIP table to begin fetching the target instruction(s).The purpose of the prediction of target addresses is so that in the usual case instructions following a transfer can be executed at a rate of one instruction per pipeline cycle regardless of the pipeline depth or the frequency of transfers. Instructions are fetched two words at a time in order that the instruction fetch unit can stay ahead of the central execution pipeline. An instruction stack is provided for purposes of buffering double words of instructions fetched by the instruction fetch unit while waiting for execution by the central execution pipeline unit. The TIP table is updated based upon the actual execution of instructions by the central execution pipeline unit, and the correctness of the TIP table predictions is checked during execution of every instruction.

摘要翻译： 用于为通用数字数据处理系统的流水线中央处理器单元预取指令的方法和装置。 为了根据执行这些指令的过去历史来预测传送和间接指令的目标地址，维护表。 预取机制形成指令地址并且与由中央处理器单元的中央执行流水线单元执行先前获取的指令并行地获取指令。 当指令被预取时，检查传输和间接预测（TIP）表以确定那些指令的过去历史。 如果没有发现传输或间接，则预取将继续进行。 如果发现传输或间接指令，则预取使用TIP表中的信息开始获取目标指令。 目标地址的预测目的是为了在通常的情况下，无论流水线深度或传输频率如何，通常可以以每个流水线周期的一个指令的速率执行传送之后的指令。 指令一次取两个字，以便指令提取单元可以保持在中央执行管线之前。 提供指令堆栈用于缓冲​​由指令获取单元取得的指令的双字，同时等待中央执行流水线单元的执行。 TIP表基于中央执行流水线单元的指令的实际执行而被更新，并且在执行每个指令期间检查TIP表预测的正确性。

公开(公告)号：US4245304A

公开(公告)日：1981-01-13

申请号：US968312

申请日：1978-12-11

申请人： Marion G. Porter ,  Robert W. Norman, Jr. ,  William A. Shelly

发明人： Marion G. Porter ,  Robert W. Norman, Jr. ,  William A. Shelly

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0859 ,  G06F12/0846 ,  G06F12/0855

摘要： A cache system includes a high speed storage unit organized into a plurality of levels, each including a number of multiword blocks and at least one multiposition address selection switch and address register. The address switch is connected to receive address signals from a plurality of address sources. The system further includes a directory organized into a plurality of levels for storing address information required for accessing blocks from the cache storage unit and timing circuits for defining first and second halves of a cache cycle of operation. Control circuits coupled to the timing circuits generate control signals for controlling the operation of the address selection switch. During the previous cycle, the control circuits condition the address selector switch to select an address which is loaded into the address register during the previous half cycle. This enables either the accessing of instructions from cache or the writing of data into cache during the first half of the next cache cycle. During the first half of the cycle, the address selected by the address switch in response to control signals from the control circuits is clocked into the address register. This permits processor operations, such as the accessing of operand data or the writing of data into cache to be performed during the second half of the same cycle.

摘要翻译： 缓存系统包括组织成多个级别的高速存储单元，每个级别包括多个多个块和至少一个多位地址选择开关和地址寄存器。 地址开关被连接以从多个地址源接收地址信号。 该系统还包括组织成多个级别的目录，用于存储从高速缓存存储单元访问块所需的地址信息和用于定义高速缓存操作周期的第一和第二半的定时电路。 耦合到定时电路的控制电路产生用于控制地址选择开关的操作的控制信号。 在上一个周期期间，控制电路使地址选择器开关状态选择在前半个周期内加载到地址寄存器中的地址。 这可以在下一个高速缓存周期的前一半期间访问来自高速缓存的指令或将数据写入高速缓存。 在周期的前一半期间，地址开关响应于来自控制电路的控制信号选择的地址被计时到地址寄存器中。 这允许诸如访问操作数数据或将数据写入高速缓存的处理器操作在相同周期的后半段期间执行。

公开(公告)号：US4208716A

公开(公告)日：1980-06-17

申请号：US968521

申请日：1978-12-11

申请人： Marion G. Porter ,  William A. Shelly ,  Robert W. Norman, Jr.

发明人： Marion G. Porter ,  William A. Shelly ,  Robert W. Norman, Jr.

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0855 ,  G06F12/0846 ,  G06F12/0859

摘要： A cache system includes a storage unit organized into a plurality of levels, each including a number of multiword blocks and a corresponding number of address selection switches and address registers. Each address selection switch has a plurality of different positions connected to receive address signals from a plurality of address sources. A decoder circuit generates output signals for controlling the operation of the address selection switches. In response to previously defined level signals, the decoder circuit conditions a specified one of the number of switches to switch from a first position to a second position. An address specifying the location into which memory data is to be written is clocked into one address register while the address specifying the location from which an instruction is to be fetched is clocked into the remaining address registers. A comparator circuit compares signals indicating the level into which memory data is to be written with signals indicating the level from which a next instruction is to be fetched. The comparator circuit generates signals which cause the delay of instruction access when there is a conflict between writing memory data and accessing instructions.

摘要翻译： 缓存系统包括组织成多个级别的存储单元，每个级别包括多个字块数量和相应数量的地址选择开关和地址寄存器。 每个地址选择开关具有连接以从多个地址源接收地址信号的多个不同位置。 解码器电路产生用于控制地址选择开关的操作的输出信号。 响应于先前定义的电平信号，解码器电路调节从第一位置切换到第二位置的开关数目中指定的一个。 指定要写入存储器数据的位置的地址被计时到一个地址寄存器中，而指定要从其获取指令的位置的地址被计时到其余的地址寄存器中。 比较器电路将指示要写入的存储器数据的电平的信号与指示下一条指令要从其获取的电平的信号进行比较。 当写入存储器数据和访问指令之间存在冲突时，比较器电路产生导致指令访问延迟的信号。

公开(公告)号：US3976977A

公开(公告)日：1976-08-24

申请号：US562317

申请日：1975-03-26

申请人： Marion G. Porter ,  Garvin Wesley Patterson ,  William A. Shelly ,  Nicolas S. Lemak

发明人： Marion G. Porter ,  Garvin Wesley Patterson ,  William A. Shelly ,  Nicolas S. Lemak

IPC分类号： G06F13/12 ,  G06F3/00 ,  G06F15/20

CPC分类号： G06F13/124

摘要： An input-output processing system (IOPS) which performs both the communication and control functions in a large scale data processing system is disclosed. By relieving the main data processor of these functions more efficient use of the entire system is made possible. The IOPS includes a processor to develop addresses for a paged memory and institute execution of input-output command sequences.

摘要翻译： 公开了一种在大规模数据处理系统中执行通信和控制功能的输入输出处理系统（IOPS）。 通过减轻这些功能的主数据处理器，可以更有效地使用整个系统。 IOPS包括处理器，用于开发分页存储器的地址并执行输入 - 输出命令序列。

公开(公告)号：US06249880B1

公开(公告)日：2001-06-19

申请号：US09156378

申请日：1998-09-17

申请人： William A. Shelly ,  Charles P. Ryan

发明人： William A. Shelly ,  Charles P. Ryan

IPC分类号： H02H305

CPC分类号： G06F11/24 ,  G06F11/2242

摘要： Interactions among multiple processors (92) are exhaustively tested. A master processor (92) retrieves test information for a set of tests from a test table (148). It then enters a series of embedded loops, with one loop for each of the tested processors (92). A cycle delay count for each of the tested processors (92) is incremented (152, 162, 172) through a range specified in the test table entry. For each combination of cycle delay count loop indices, a single test is executed (176). In each such test (176), the master processor (92) sets up (182) each of the other processors (92) being tested. This setup (182) specifies the delay count and the code for that processor (92) to execute. When each processor (92) is setup (182), it waits (192) for a synchronize interrupt (278). When all processors (92) have been setup (182), the master processor (92) issues (191) the synchronize interrupt signal (276). Each processor (92) then starts traces (193) and delays (194) the specified number of cycles. After the delay, the processor (92) executes its test code (195).

摘要翻译： 多处理器之间的相互作用（92）进行了详尽的测试。 主处理器（92）从测试表（148）检索一组测试的测试信息。 然后，它进入一系列嵌入式循环，每个测试处理器（92）有一个循环。 每个测试处理器（92）的周期延迟计数通过测试表条目中指定的范围递增（152,162,172）。 对于循环延迟计数循环指标的每个组合，执行单个测试（176）。 在每个这样的测试（176）中，主处理器（92）建立（182）被测试的每个其他处理器（92）。 该设置（182）指定延迟计数和该处理器（92）执行的代码。 当每个处理器（92）被建立（182）时，它等待（192）同步中断（278）。 当所有处理器（92）已经建立（182）时，主处理器（92）发出（191）同步中断信号（276）。 每个处理器（92）然后开始指定数量的循环的迹线（193）和延迟（194）。 在延迟之后，处理器（92）执行其测试代码（195）。

公开(公告)号：US06230263B1

公开(公告)日：2001-05-08

申请号：US09156376

申请日：1998-09-17

申请人： Charles P. Ryan ,  Ronald W. Yoder ,  William A. Shelly

发明人： Charles P. Ryan ,  Ronald W. Yoder ,  William A. Shelly

IPC分类号： G06F930

CPC分类号： G06F9/30079

摘要： A processor (92) in a data processing system (80) provides a DELAY instruction. Executing the DELAY instruction causes the processor (92) to a specified integral number of clock (98) cycles before continuing. Delays are guaranteed to have a linear relationship with a constant slope with the specified number of clock cycles. Incrementing the specified delay through a range allows exhaustive testing of interactions among multiple processors.

摘要翻译： 数据处理系统（80）中的处理器（92）提供DELAY指令。 执行DELAY指令使处理器（92）在指定的整数时钟（98）周期之前继续。 延迟保证与具有指定时钟周期数的恒定斜率具有线性关系。 通过一个范围增加指定的延迟允许对多个处理器之间的交互进行详尽的测试。

公开(公告)号：US6052700A

公开(公告)日：2000-04-18

申请号：US156104

申请日：1998-09-17

申请人： Clinton B. Eckard ,  William A. Shelly

发明人： Clinton B. Eckard ,  William A. Shelly

IPC分类号： G06F1/12 ,  G06F1/14 ,  G06F12/08

CPC分类号： G06F11/26 ,  G06F11/2242 ,  G06F11/24 ,  G06F1/14 ,  G06F12/0833

摘要： Each processor (92) in a data processing system (80) caches a copy of the master calendar clock (97). The master calendar clock (97) and all of the cached calendar clocks (272) are periodically incremented utilizing a common clock (99). Whenever a processor (92) in the system (80) loads the master calendar clock (97) with a new value, that processor (92) broadcasts a cached calendar clock updated interrupt signal (276) to all of the processors in the system. In response to this interrupt (278), each processor (92) clears its cached calendar clock valid flag (274). Whenever a read calendar clock instruction is executed on a processor (92), the flag (274) is tested, and if set, its cached calendar clock (272) value is returned. Otherwise, the master calendar clock (97) value is retrieved, written to that processor's cached calendar clock (272), and returned. The cached calendar clock valid flag (274) is set to indicate a valid cached calendar clock (272).

摘要翻译： 数据处理系统（80）中的每个处理器（92）缓存主日历时钟（97）的副本。 使用公共时钟（99）来周期性地增加主日历时钟（97）和所有缓存的日历时钟（272）。 只要系统（80）中的处理器（92）以新值加载主日历时钟（97），该处理器（92）向系统中的所有处理器广播高速缓存的日历时钟更新的中断信号（276）。 响应于该中断（278），每个处理器（92）清除其缓存的日历时钟有效标志（274）。 每当在处理器（92）上执行读取日历时钟指令时，测试标志（274），并且如果被设置，则返回其高速缓存的日历时钟（272）值。 否则，检索主日历时钟（97）值，写入该处理器的缓存日历时钟（272）并返回。 高速缓存的日历时钟有效标志（274）被设置为指示有效的高速缓存日历时钟（272）。

公开(公告)号：US5515529A

公开(公告)日：1996-05-07

申请号：US218538

申请日：1994-03-25

申请人： William A. Shelly ,  Ronald E. Lange ,  Donald C. Boothroyd

发明人： William A. Shelly ,  Ronald E. Lange ,  Donald C. Boothroyd

IPC分类号： G06F11/10 ,  G06F11/16 ,  G06F12/08 ,  G06F15/40

CPC分类号： G06F11/1633 ,  G06F11/10 ,  G06F12/0802

摘要： In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, a first BPU transfers to cache storage only the even bits of a given data manipulation result, and a second BPU correspondingly transfers to cache storage only the odd bit information of the result. One BPU segregates the even bits of the result, adds parity information and sends the even bits and parity information to the cache unit. Similarly, the second BPU segregates the odd bits of the result, adds parity information and sends the odd bits and parity information to the cache unit. In the cache unit, the even and odd bit information are separately parity checked before storage into cache memory. If a parity error is observed in either set of information, an error signal is issued to institute appropriate remedial action.

摘要翻译： 为了验证在一个CPU中的数据操作结果，该CPU结合了重复的BPU以完整性，哪些BPU通常在单个VLSI电路芯片上实现，并且能够执行单精度和双精度数据操作操作，第一个BPU传输到缓存 仅存储给定数据操作结果的偶数位，并且第二BPU相应地将仅结果的奇数位信息传输到高速缓存存储器。 一个BPU分离结果的偶数位，添加奇偶校验信息，并将偶数位和奇偶校验信息发送到高速缓存单元。 类似地，第二BPU分离结果的奇数比特，添加奇偶校验信息，并将奇数比特和奇偶校验信息发送到高速缓存单元。 在高速缓存单元中，偶数和奇数比特信息在存储到高速缓冲存储器中之前被单独校验。 如果在任一组信息中观察到奇偶校验错误，则发出错误信号以进行适当的补救措施。

公开(公告)号：US5495579A

公开(公告)日：1996-02-27

申请号：US218532

申请日：1994-03-25

申请人： William A. Shelly ,  Ronald E. Lange ,  Donald C. Boothroyd

发明人： William A. Shelly ,  Ronald E. Lange ,  Donald C. Boothroyd

IPC分类号： G06F11/10 ,  G06F11/16 ,  G06F11/00

CPC分类号： G06F11/1654 ,  G06F11/10 ,  G06F11/1633

摘要： In order to validate data manipulation results in a CPU which incorporates duplicate basic processing units or integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation to obtain first and second data manipulation results, which should be identical, and a cache unit for receiving data manipulation results from both BPUs and for transferring specified information words simultaneously to both BPUs upon request. These operations are controlled by cache interface control signals identically generated in each BPU. In each BPU, the control signals are arranged into first and second groups which are nominally identical. The first control signal group is transmitted to the cache unit from one BPU while the second control group is transmitted to the cache unit from the other BPU. In each BPU, parity is generated for each control group separately. Parity for the group sent to the cache unit by each BPU is included with the control signal information for checking in the cache unit. Parity for the group not sent to the cache unit by each BPU is transmitted to the other BPU and checked against the locally generated parity for that group. In the event of a parity miscompare sensed in either BPU or a parity error sensed in the cache unit, an error signal is issued to institute appropriate remedial action.

摘要翻译： 为了验证包含重复基本处理单元或完整性的CPU中的数据处理结果，哪些BPU通常在单个VLSI电路芯片上实现，并且能够执行单精度和双精度数据操作以获得第一和第二数据 操作结果应该相同，以及用于从两个BPU接收数据操作结果并根据请求同时传送指定的信息字的缓存单元。 这些操作由在每个BPU中相同生成的高速缓存接口控制信号控制。 在每个BPU中，控制信号被布置成名义上相同的第一和第二组。 第一控制信号组从一个BPU发送到高速缓存单元，而第二控制组从另一个BPU发送到高速缓存单元。 在每个BPU中，分别为每个控制组生成奇偶校验。 用于由每个BPU发送到高速缓存单元的组的奇偶校验包括用于检查高速缓存单元的控制信号信息。 每个BPU未发送到高速缓存单元的组的奇偶校验被发送到另一个BPU，并针对该组的本地生成的奇偶校验进行检查。 在BPU中感测到的奇偶校验误差或在高速缓存单元中感测到的奇偶校验错误的情况下，发出错误信号以进行适当的补救动作。