公开(公告)号：US06342423B1

公开(公告)日：2002-01-29

申请号：US09667781

申请日：2000-09-22

Applicant: Emi Ishida ,  Srinath Krishnan ,  Ming Yin Hao ,  Effiong Ibok

Inventor： Emi Ishida ,  Srinath Krishnan ,  Ming Yin Hao ,  Effiong Ibok

IPC: H01L218238

CPC classification number: H01L29/6653 ,  H01L21/823468 ,  H01L21/8238 ,  H01L29/6659 ,  H01L29/7833

Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which is readily etched in its as-deposited, undensified state but difficult-to-etch in its thermally annealed, densified state. The as-deposited, undensified spacers are removed by etching with dilute aqueous HF after implantation of heavily-sloped source/drain junction regions but prior to annealing of the implant for dopant diffusion/activation and lattice damage relaxation. Lightly-or moderately doped, shallow-depth source/drain extensions are implanted and annealed after spacer removal.

Abstract translation: 亚微米尺寸的MOS和/或CMOS晶体管通过采用由诸如UV氮化物的材料制成的可移除的侧壁间隔的工艺制造，其易于以其沉积的未增稠的状态蚀刻，但在其热 退火，致密化状态。 通过在植入重度倾斜的源极/漏极结区域之后但是在用于掺杂剂扩散/激活和晶格损伤弛豫的植入物退火之前通过用稀的HF水溶液来蚀刻沉积的未增强的间隔物。 轻微或中度掺杂的浅深度源极/漏极延伸部分在移除间隔物之后被植入和退火。

公开(公告)号：US06265291B1

公开(公告)日：2001-07-24

申请号：US09224754

申请日：1999-01-04

Applicant: Bin Yu ,  Emi Ishida

Inventor： Bin Yu ,  Emi Ishida

IPC: H01L2104

CPC classification number: H01L21/28518 ,  H01L21/26506

Abstract: A method of manufacturing an integrated circuit to optimize the contact resistance between impurity diffusing layers and silicide is disclosed herein. The method includes implanting a first material to a layer of semiconductor to create a buried amorphous silicon layer; implanting a second material in the layer of semiconductor and buried amorphous layer, forming a dopant profile region with a curved shape; depositing a layer of metal on the layer of semiconductor; melting the buried amorphous layer to reconfigure the curved shape to a substantially vertical profile of maximum dopant concentration; and forming silicide with the layer of semiconductor and layer of metal, the bottom of the silicide located in the vertical shape on the dopant profile region.

Abstract translation: 本文公开了制造用于优化杂质扩散层和硅化物之间的接触电阻的集成电路的方法。 该方法包括将第一材料注入到半导体层中以产生埋入的非晶硅层; 将第二材料注入到半导体层和埋入非晶层中，形成具有弯曲形状的掺杂剂分布区域; 在半导体层上沉积金属层; 熔化埋入的非晶层以将弯曲形状重新配置为最大掺杂剂浓度的基本垂直分布; 并且用半导体层和金属层形成硅化物，硅化物的底部位于掺杂物分布区域上的垂直形状。

公开(公告)号：US6040019A

公开(公告)日：2000-03-21

申请号：US799230

申请日：1997-02-14

Applicant: Emi Ishida ,  Xiao-Yu Li ,  Sunil D. Mehta

Inventor： Emi Ishida ,  Xiao-Yu Li ,  Sunil D. Mehta

IPC: H01L21/265 ,  H01L21/268 ,  H01L21/8247 ,  C23C14/00 ,  B05D3/06 ,  H01L21/263

CPC classification number: H01L27/11521 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L27/11558

Abstract: A method of forming a region of impurity in a semiconductor substrate with minimal damage. The method includes the steps of: forming a reaction-inhibiting impurity region in the semiconductor substrate to a depth below the semiconductor substrate; and applying laser energy to the semiconductor substrate at a sufficient magnitude to liquify the semiconductor substrate in the region.

Abstract translation: 一种以最小的损伤在半导体衬底中形成杂质区域的方法。 该方法包括以下步骤：在半导体衬底的深度下方形成反应抑制杂质区; 以及将激光能量以足够大的量施加到所述半导体衬底以在所述区域中液化所述半导体衬底。

公开(公告)号：US07041714B2

公开(公告)日：2006-05-09

申请号：US10467862

申请日：2002-10-07

Applicant: Hiroshi Takeshita ,  Emi Ishida ,  Hideki Kazama

Inventor： Hiroshi Takeshita ,  Emi Ishida ,  Hideki Kazama

IPC: A61K6/83 ,  A61C5/00

CPC classification number: A61K6/0091 ,  A61K6/0835 ,  C08L33/08 ,  C08L33/10 ,  C08L25/16 ,  A61K6/0023

Abstract: A dental adhesive containing an acidic group-containing radically polymerizable monomer, a non-acidic radically polymerizable monomer, a chemical polymerization initiator and a filler, as well as a 2,4-diphenyl-4-methyl-1-pentene. When the dental adhesive is used for adhering a crown restorative to the tooth, an excess of cement swelling from the surface of adhesion can be favorably removed, the curing time can be suitably adjusted without decreasing the strength of adhesion to the tooth, and a change in the color tone of the cured body can be effectively suppressed.

Abstract translation: 含有含酸性基团的自由基聚合性单体，非酸性自由基聚合性单体，化学聚合引发剂和填料以及2,4-二苯基-4-甲基-1-戊烯的牙科用粘合剂。 当牙科粘合剂用于将牙冠固定到牙齿上时，可以有利地去除从粘附表面渗出的过量的水泥溶胀，可以适当地调节固化时间，而不降低对牙齿的粘附强度，并且改变 可以有效地抑制固化体的色调。

公开(公告)号：US06506640B1

公开(公告)日：2003-01-14

申请号：US09667686

申请日：2000-09-22

Applicant: Emi Ishida ,  Deepak K. Nayak ,  Ming Yin Hao

Inventor： Emi Ishida ,  Deepak K. Nayak ,  Ming Yin Hao

IPC: H01L218238

CPC classification number: H01L21/26513 ,  H01L21/823807 ,  H01L29/105 ,  H01L29/1083

Abstract: Submicron-dimensioned, MOSFET devices are formed using multiple implants for forming an impurity concentration distribution profile exhibiting three impurity concentration peaks at a predetermined depths below the semiconductor surface substrate. The inventive method reduces “latch-up” and “punch-through” with controllable adjustment of the threshold voltage.

Abstract translation: 亚微米尺寸的MOSFET器件使用多个注入形成，用于形成在半导体表面衬底下方的预定深度处显示三个杂质浓度峰的杂质浓度分布分布。 本发明的方法通过可控地调节阈值电压来减少“闭锁”和“穿通”。

公开(公告)号：US06482725B1

公开(公告)日：2002-11-19

申请号：US09640083

申请日：2000-08-17

Applicant: Emi Ishida

Inventor： Emi Ishida

IPC: H01L2126

CPC classification number: H01L29/4916 ,  H01L21/28035 ,  H01L21/76254

Abstract: Depletion of dopant from polysilicon gate layers with attendant dopant penetration of underlying gate oxide layers of silicon-based MOS and CMOS transistor devices are reduced or substantially eliminated by a process wherein a thin, high-quality silicon oxide gate insulator layer initially formed on a surface of a heavily-doped polysilicon substrate. The oxide layer is then subjected to impurity ion implantation selected to penetrate a desired depth into the underlying semiconductor substrate for formation of a structurally weakened cleavage plane thereat. The cleaved substrate is then bonded, via the silicon oxide gate insulator layer, to a second, lightly- to moderately-doped semiconductor substrate of similar conductivity type. The thus-produced composite is then subjected to further processing for patterning of the heavily-doped gate and gate insulator layers and to define active areas for formation of source/drain regions in the second, lightly-doped substrate.

Abstract translation: 通过其中最初形成在表面上的薄的高质量的氧化硅栅极绝缘体层的工艺来减少或基本上消除了由硅基MOS和CMOS晶体管器件的底层栅极氧化物层伴随的掺杂剂穿透的多晶硅栅极层的掺杂剂的消耗， 的重掺杂多晶硅衬底。 然后对氧化物层进行杂质离子注入，以将穿透期望的深度渗入下面的半导体衬底中，以在其上形成结构弱化的解理面。 然后将经裂解的衬底经由氧化硅栅极绝缘体层接合到具有相似导电类型的第二，轻微至中等掺杂的半导体衬底。 然后对由此产生的复合材料进行进一步处理，以对重掺杂的栅极和栅极绝缘体层进行构图，并且限定在第二轻掺杂衬底中形成源/漏区的有源区。

公开(公告)号：US06475868B1

公开(公告)日：2002-11-05

申请号：US09640082

申请日：2000-08-17

Applicant: Ming Yin Hao ,  Asim Selcuk ,  Richard P. Rouse ,  Emi Ishida

Inventor： Ming Yin Hao ,  Asim Selcuk ,  Richard P. Rouse ,  Emi Ishida

IPC: H01L2100

CPC classification number: H01L29/665 ,  H01L21/26506 ,  H01L21/26533 ,  H01L29/0847

Abstract: Silicon-based, submicron-dimensioned MOS and/or CMOS transistor devices having substantially reduced source/drain junction-to-semiconductor substrate capacitance are formed by implanting oxygen atoms and/or molecules just below source/drain implant regions. Implantation conditions are selected to provide a peak oxygen implant concentration at a depth just below the ultimate source/drain junction depth. Subsequent thermal processing at elevated temperature results in source/drain dopant diffusion/activation and formation of a silicon oxide barrier layer or stratum just below the ultimate source/drain junction depth, thereby substantially reducing junction-to-substrate capacitance of refractory metal silicide-contact devices.

Abstract translation: 通过在原始/漏极注入区域下方注入氧原子和/或分子，形成具有基本上减少的源极/漏极结至半导体衬底电容的基于硅的亚微米尺寸的MOS和/或CMOS晶体管器件。 选择植入条件以在刚好低于最终源极/漏极结深度的深度处提供峰值氧注入浓度。 随后在高温下的热处理导致源极/漏极掺杂剂扩散/激活并形成刚好低于最终源极/漏极结深度的氧化硅阻挡层或层，从而大大降低难熔金属硅化物接触的结到衬底的电容 设备。

公开(公告)号：US06429083B1

公开(公告)日：2002-08-06

申请号：US09598797

申请日：2000-06-21

Applicant: Emi Ishida ,  Srinath Krishnan ,  Ming Hao ,  Effiong Ibok

Inventor： Emi Ishida ,  Srinath Krishnan ,  Ming Hao ,  Effiong Ibok

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which has been treated subsequent to its deposition, e.g., by ion implantation, to augment its etch rate with a room temperature etchant, e.g., dilute aqueous HF. The treated spacers are removed with the dilute, aqueous HF after implantation of moderately or heavily-doped source/drain regions but prior to any post-implantation annealing processing, in order not to increase the etch resistance of the spacer material by thermally-induced densification.

Abstract translation: 亚微米尺寸的MOS和/或CMOS晶体管通过采用由诸如UV氮化物的材料制成的可移除侧壁间隔的工艺来制造，其已经在其沉积之后被处理，例如通过离子注入，以增加其蚀刻速率以增加其蚀刻速率 室温蚀刻剂，例如稀释的HF水溶液。 在植入中等或重掺杂的源极/漏极区域之后但在任何植入后退火处理之后，用稀的HF水溶液去除经处理的间隔物，以便通过热致密化而不增加间隔物材料的耐蚀刻性 。

公开(公告)号：US06344396B1

公开(公告)日：2002-02-05

申请号：US09667601

申请日：2000-09-22

Applicant: Emi Ishida ,  Srinath Krishman ,  Ming Yin Hao ,  Effiong Ibok

Inventor： Emi Ishida ,  Srinath Krishman ,  Ming Yin Hao ,  Effiong Ibok

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L29/6656 ,  H01L29/66659

Abstract: Sub-micron-dimensioned, asymmetrically-configured MOS and/or CMOS transistors are fabricated using removable sidewall spacers made of a material, such as UV-nitride, one of which is selectively treated subsequent to deposition, e.g., by ion implantation, to augment the etch rate thereof with a room temperature etchant, e.g., dilute aqueous HF. The treated spacer is removed with the dilute, aqueous HF prior to implantation of asymmetrically-configured, moderately or heavily-doped source/drain regions but prior to any post-implantation annealing processing, in order not to increase the etch resistance of the spacer material by thermally-induced densification.

Abstract translation: 亚微米尺寸的非对称配置的MOS和/或CMOS晶体管使用由诸如UV氮化物的材料制成的可拆卸的侧壁间隔来制造，其中一个隔离层在沉积之后例如通过离子注入被选择性地处理以增加 其用室温蚀刻剂的蚀刻速率，例如稀释的HF水溶液。 在注入不对称配置的中等或高掺杂源/漏区之前，但在任何植入后退火处理之前，用稀的HF水溶液去除经处理的间隔物，以便不增加间隔物材料的耐蚀刻性 通过热致密化。

公开(公告)号：US06316319B1

公开(公告)日：2001-11-13

申请号：US09357330

申请日：1999-07-20

Applicant: Emi Ishida ,  Dong-Hyuk Ju

Inventor： Emi Ishida ,  Dong-Hyuk Ju

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/2652 ,  H01L29/665

Abstract: A semiconductor device with shallow junctions is obtained by forming shallow source/drain extensions followed by forming a film over the gate electrode and the semiconductor substrate. The film is formed having a targeted thicknesses to facilitate gate electrode doping and source/drain formation. Ion implantation is then conducted to fully dope the gate electrode and form moderately or heavily doped source/drain implants, thereby reducing gate depletion.

Abstract translation: 通过形成浅的源极/漏极延伸部分，然后在栅电极和半导体衬底上形成膜，获得具有浅结的半导体器件。 形成具有目标厚度的膜以便于栅电极掺杂和源极/漏极形成。 然后进行离子注入以完全掺杂栅电极并形成适度或重掺杂的源极/漏极注入，从而减少栅极耗尽。