公开(公告)号：US07790561B2

公开(公告)日：2010-09-07

申请号：US11173088

申请日：2005-07-01

申请人： Richard P. Rouse ,  Shashank S. Ekbote ,  Haowen Bu

发明人： Richard P. Rouse ,  Shashank S. Ekbote ,  Haowen Bu

IPC分类号： H01L21/336

CPC分类号： H01L21/823468 ,  H01L21/3185 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

摘要： The present invention provides a method for manufacturing a semiconductor device, a semiconductor device, and a method for manufacturing an integrated circuit including a semiconductor device. The method for manufacturing the semiconductor device, without limitation, may include providing a gate dielectric layer (413, 423) and a gate electrode layer (418, 428) over a substrate (310), and forming a gate sidewall spacer (610, 630) along one or more sidewalls of the gate dielectric layer (413, 423) and the gate electrode layer (418, 428) using a plasma enhanced chemical vapor deposition process, and forming different hydrogen concentration in NMOS and PMOS sidewall spacers (610, 630) using a local hydrogen treatment (LHT) method.

摘要翻译： 本发明提供一种制造半导体器件的方法，半导体器件以及包括半导体器件的集成电路的制造方法。 制造半导体器件的方法，但不限于，可以包括在衬底（310）上方提供栅极电介质层（413,423）和栅极电极层（418,428），并且形成栅极侧壁间隔物 ），使用等离子体增强化学气相沉积工艺在栅极电介质层（413,423）和栅极电极层（418,428）的一个或多个侧壁上形成，并且在NMOS和PMOS侧壁间隔物（610,630）中形成不同的氢浓度 ）使用局部氢处理（LHT）方法。

公开(公告)号：US20070004156A1

公开(公告)日：2007-01-04

申请号：US11173088

申请日：2005-07-01

申请人： Richard P. Rouse ,  Shashank S. Ekbote ,  Haowen Bu

发明人： Richard P. Rouse ,  Shashank S. Ekbote ,  Haowen Bu

IPC分类号： H01L21/336

CPC分类号： H01L21/823468 ,  H01L21/3185 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

摘要： The present invention provides a method for manufacturing a semiconductor device, a semiconductor device, and a method for manufacturing an integrated circuit including a semiconductor device. The method for manufacturing the semiconductor device, without limitation, may include providing a gate dielectric layer (413, 423) and a gate electrode layer (418, 428) over a substrate (310), and forming a gate sidewall spacer (610, 630) along one or more sidewalls of the gate dielectric layer (413, 423) and the gate electrode layer (418, 428) using a plasma enhanced chemical vapor deposition process, and forming different hydrogen concentration in NMOS and PMOS sidewall spacers (610, 630) using a local hydrogen treatment (LHT) method.

摘要翻译： 本发明提供一种制造半导体器件的方法，半导体器件以及包括半导体器件的集成电路的制造方法。 制造半导体器件的方法，但不限于，可以包括在衬底（310）上方提供栅极电介质层（413,423）和栅极电极层（418,428），并且形成栅极侧壁间隔物 ），使用等离子体增强化学气相沉积工艺在栅极电介质层（413,423）和栅极电极层（418,428）的一个或多个侧壁上形成，并且在NMOS和PMOS侧壁间隔物（610,630）中形成不同的氢浓度 ）使用局部氢处理（LHT）方法。

公开(公告)号：US06531347B1

公开(公告)日：2003-03-11

申请号：US09776713

申请日：2001-02-06

申请人： Carl R. Huster ,  Judy An ,  Richard P. Rouse

发明人： Carl R. Huster ,  Judy An ,  Richard P. Rouse

IPC分类号： H01L2184

CPC分类号： H01L29/66636

摘要： The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming source and drain regions that are recessed a prescribed depth below the main surface of the semiconductor substrate. Sidewall spacers and a silicide layer are subsequently formed on the gate electrode stack. The resulting semiconductor device exhibits reduced capacitance between the gate electrode and the source/drain regions, while maintaining circuit reliability.

摘要翻译： 通过形成在半导体衬底的主表面下方以规定深度凹陷的源极和漏极区域来减小半导体器件的栅极电极和源极/漏极区域之间的电容。 随后在栅极电极堆叠上形成侧壁间隔物和硅化物层。 所得到的半导体器件在保持电路可靠性的同时，在栅极电极和源极/漏极区域之间表现出减小的电容。

公开(公告)号：US06475868B1

公开(公告)日：2002-11-05

申请号：US09640082

申请日：2000-08-17

申请人： Ming Yin Hao ,  Asim Selcuk ,  Richard P. Rouse ,  Emi Ishida

发明人： Ming Yin Hao ,  Asim Selcuk ,  Richard P. Rouse ,  Emi Ishida

IPC分类号： H01L2100

CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/26533 ,  H01L29/0847

摘要： Silicon-based, submicron-dimensioned MOS and/or CMOS transistor devices having substantially reduced source/drain junction-to-semiconductor substrate capacitance are formed by implanting oxygen atoms and/or molecules just below source/drain implant regions. Implantation conditions are selected to provide a peak oxygen implant concentration at a depth just below the ultimate source/drain junction depth. Subsequent thermal processing at elevated temperature results in source/drain dopant diffusion/activation and formation of a silicon oxide barrier layer or stratum just below the ultimate source/drain junction depth, thereby substantially reducing junction-to-substrate capacitance of refractory metal silicide-contact devices.

摘要翻译： 通过在原始/漏极注入区域下方注入氧原子和/或分子，形成具有基本上减少的源极/漏极结至半导体衬底电容的基于硅的亚微米尺寸的MOS和/或CMOS晶体管器件。 选择植入条件以在刚好低于最终源极/漏极结深度的深度处提供峰值氧注入浓度。 随后在高温下的热处理导致源极/漏极掺杂剂扩散/激活并形成刚好低于最终源极/漏极结深度的氧化硅阻挡层或层，从而大大降低难熔金属硅化物接触的结到衬底的电容 设备。

公开(公告)号：US06225170B1

公开(公告)日：2001-05-01

申请号：US09428481

申请日：1999-10-28

申请人： Effiong Ibok ,  Richard P. Rouse

发明人： Effiong Ibok ,  Richard P. Rouse

IPC分类号： H01L21336

CPC分类号： H01L29/66568 ,  H01L21/28518 ,  H01L29/665

摘要： In order to form a self-aligned damascene gate with an attendant contact or contacts, a thick layer of dielectric material is formed over a semiconductor substrate in which drain and source regions have previously been implanted and annealed. This dielectric layer is polished for planarity, a combined gate and contact mask is used to pattern the dielectric, and the interlayer dielectric is etched and the resist is stripped. The gate dielectric is deposited and polysilicon is then deposited over the dielectric and doped by implantation and then annealed. This polysilicon layer is polished to the dielectric level. The wafer is then masked to cover the gate and the polysilicon is anisotropically etched off in the contact areas. The exposed polysilicon at the gate site and the silicon exposed at the contact site are then salicided.

摘要翻译： 为了形成具有伴随的接触或接触的自对准镶嵌栅极，在半导体衬底上形成厚的介电材料层，其中漏极和源极区域先前被植入和退火。 为了平坦化而抛光该电介质层，使用组合的栅极和接触掩模对电介质进行图案化，并且蚀刻层间电介质并剥离抗蚀剂。 沉积栅极电介质，然后将多晶硅沉积在电介质上并通过注入掺杂，然后退火。 该多晶硅层被抛光到介电层。 然后将晶片掩蔽以覆盖栅极，并且多晶硅在接触区域中各向异性地蚀刻掉。 然后将在栅极处暴露的多晶硅和在接触部位暴露的硅浸渍。

公开(公告)号：US20100275170A1

公开(公告)日：2010-10-28

申请号：US12768139

申请日：2010-04-27

申请人： Narayanasamy Subramanian ,  Richard P. Rouse ,  Ziding Yue

发明人： Narayanasamy Subramanian ,  Richard P. Rouse ,  Ziding Yue

IPC分类号： G06F17/50

CPC分类号： G06F17/5063 ,  G06F17/5068

摘要： A computer-based method of converting an analog integrated circuit design from a source technology to a target technology, by providing a computer readable source schematic file and a computer readable source layout file for the analog integrated circuit design in the source technology, providing a computer readable technology transfer file that includes conversion tables between properties of the source technology and properties of the target technology, converting the source schematic file in the source technology to a target schematic file in the target technology with the computer using the technology transfer file, and converting the source layout file in the source technology to a target layout file in the target technology with the computer using the technology transfer file.

摘要翻译： 一种基于计算机的将模拟集成电路设计从源技术转换为目标技术的方法，通过提供用于源技术中的模拟集成电路设计的计算机可读源原理图文件和计算机可读源布局文件，提供计算机 包括源技术的属性和目标技术属性之间的转换表，将源技术中的源原理图文件转换为目标技术中的目标原理图文件，并使用计算机使用技术传输文件，并转换 源码文件在源码技术中以目标布局文件的目标技术与计算机使用技术传输文件。

公开(公告)号：US07064043B1

公开(公告)日：2006-06-20

申请号：US11008007

申请日：2004-12-09

申请人： Richard P. Rouse

发明人： Richard P. Rouse

IPC分类号： H01L21/20 ,  H01L21/8242

CPC分类号： H01L29/94 ,  H01L23/481 ,  H01L23/50 ,  H01L29/66189 ,  H01L2924/0002 ,  H01L2924/00

摘要： A technique for forming a MOS capacitor (100) that can be utilized as a decoupling capacitor is disclosed. The MOS capacitor (100) is formed separately from the particular circuit device (170) that it is to service. As such, the capacitor (100) and its fabrication process can be optimized in terms of efficiency, etc. The capacitor (100) is fabricated with conductive contacts (162) that allow it to be fused to the device (170) via conductive pads (172) of the device (170). As such, the capacitor (100) and device (170) can be packaged together and valuable semiconductor real estate can be conserved as the capacitor (100) is not formed out of the same substrate as the device (170). The capacitor (100) further includes deep contacts (150, 152) whereon bond pads (180, 182) can be formed that allow electrical connection of the capacitor (100) and device (170) to the outside world.

摘要翻译： 公开了一种用于形成可用作去耦电容器的MOS电容器（100）的技术。 MOS电容器（100）与要使用的特定电路装置（170）分开形成。 因此，电容器（100）及其制造工艺可以在效率等方面优化。电容器（100）由导电触点（162）制成，其允许其通过导电焊盘（170）熔合到器件（170） （172）。 这样，电容器（100）和器件（170）可以被封装在一起，并且由于电容器（100）不与器件（170）相同的衬底形成，因此可以节省有价值的半导体实际值。 电容器（100）还包括深触点（150,152），其中可以形成接合焊盘（180,182），其允许电容器（100）和设备（170）电连接到外界。

公开(公告)号：US06503801B1

公开(公告)日：2003-01-07

申请号：US09640186

申请日：2000-08-17

申请人： Richard P. Rouse ,  Che-Hoo Ng ,  Judy X. An

发明人： Richard P. Rouse ,  Che-Hoo Ng ,  Judy X. An

IPC分类号： H01L21336

CPC分类号： H01L29/66575 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/1045 ,  H01L29/66659

摘要： A semiconductor device with reduced leakage current is obtained by forming a non-uniform channel doping profile. A high impurity region of the opposite conductive type of a source region is formed between the channel region and source region by transient enhanced diffusion (TED). The high impurity region substantially reduces the threshold voltage rolling off problem.

摘要翻译： 通过形成不均匀的沟道掺杂分布来获得具有减小的漏电流的半导体器件。 通过瞬时增强扩散（TED）在沟道区域和源极区域之间形成相反导电类型的源极区域的高杂质区域。 高杂质区域大大降低了阈值电压下降的问题。

公开(公告)号：US06372582B1

公开(公告)日：2002-04-16

申请号：US09639794

申请日：2000-08-17

申请人： Richard P. Rouse ,  Ming Yin Hao ,  Emi Ishida ,  Effiong Ibok

发明人： Richard P. Rouse ,  Ming Yin Hao ,  Emi Ishida ,  Effiong Ibok

IPC分类号： H01L21336

CPC分类号： H01L29/105 ,  H01L21/223 ,  H01L21/26513

摘要： Submicron-dimensioned, silicon-based MOS-type transistor devices having reduced tendency for “latch up” are formed by removing residual indium dopant utilized for forming a retrograde-shaped indium doping concentration profile of the channel region from the surface and uppermost stratum of the silicon substrate by a rapid thermal annealing process prior to silicon oxide thin gate insulator formation. The inventive methodology substantially eliminates deleterious indium contamination of the gate insulator layer.

摘要翻译： 通过去除用于形成沟道区域的逆向形状的铟掺杂浓度分布的残留铟掺杂物，形成具有降低的“闭锁”趋势的亚微米尺寸的硅基MOS型晶体管器件， 硅衬底通过在氧化硅薄栅极绝缘体形成之前的快速热退火工艺。 本发明的方法基本上消除了栅极绝缘体层的有害的铟污染。

公开(公告)号：US06306702B1

公开(公告)日：2001-10-23

申请号：US09379627

申请日：1999-08-24

申请人： Ming Yin Hao ,  Richard P. Rouse ,  Zicheng Gary Ling

发明人： Ming Yin Hao ,  Richard P. Rouse ,  Zicheng Gary Ling

IPC分类号： H01L218238

CPC分类号： H01L21/823864 ,  H01L21/823814

摘要： CMOS transistors, i.e., N- and P-type transistors, are formed with substantially the same gate length and source/drain regions with lightly doped extensions. Embodiments include sequentially: ion implanting an N-type impurity, e.g. As, to form the N- type transistor shallow source/drain implants; forming relatively thin first sidewall spacers on the gates of both transistors; ion implanting a P-type impurity, e.g. BF2, to form shallow source/drain extension implants for the P-type transistor; forming relatively thick side wall spacers on the first sidewall spacers of both transistors; ion implanting, e.g. As, to form moderately or heavily doped N-type implants; activation annealing at a first temperature, e.g., about 1050° C. to form the shallow N- and P-type source/drain extensions and moderately or heavily doped P-type source/drain regions; ion implanting a P-type impurity, e.g., BF2, to form moderately or heavily doped P-type source/drain implants; and activation annealing at a second temperature less than the first temperature, e.g., at about 1000° C. to form moderately or heavily doped P type source/drain regions.

摘要翻译： CMOS晶体管，即N型和P型晶体管形成为具有基本上相同的栅极长度和具有轻掺杂扩展的源极/漏极区域。 实施方案包括顺序地：离子注入N型杂质，例如 为了形成N型晶体管浅源/漏植入物; 在两个晶体管的栅极上形成较薄的第一侧壁间隔物; 离子注入P型杂质。 BF2，形成P型晶体管的浅源极/漏极延伸注入; 在两个晶体管的第一侧壁间隔物上形成相对厚的侧壁间隔物; 离子注入 为了形成适度或重掺杂的N型植入物; 在第一温度例如约1050℃下进行活化退火以形成浅的N和P型源极/漏极延伸部分和适度或重掺杂的P型源极/漏极区域; 离子注入P型杂质例如BF 2，以形成适度或重掺杂的P型源极/漏极植入物; 以及在小于第一温度的第二温度例如约1000℃下进行活化退火，以形成适度或重掺杂的P型源/漏区。