公开(公告)号：US09003209B2

公开(公告)日：2015-04-07

申请号：US13538262

申请日：2012-06-29

申请人： Gregory Sizikov ,  Michael Zelikson ,  Efraim Rotem ,  Eyal Fayneh

发明人： Gregory Sizikov ,  Michael Zelikson ,  Efraim Rotem ,  Eyal Fayneh

IPC分类号： G06F1/00 ,  G05F1/00 ,  G05F3/02 ,  G06F1/26 ,  G06F1/32

CPC分类号： G06F1/324 ,  G05F3/08 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3275 ,  H02M3/158

摘要： Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.

摘要翻译： 这里描述的集成电路包括：具有一个或多个桥式驱动器的开关电压调节器（SVR），以向多个电源域提供稳定的电源; 以及功率控制单元（PCU），其可操作以根据所述多个功率域的状态来调整所述SVR的开关频率，其中所述一个或多个桥接驱动器的驱动强度或有源相位计数也由所述SVR的逻辑单元 当SVR的开关频率被调整时。

公开(公告)号：US06922047B2

公开(公告)日：2005-07-26

申请号：US10446838

申请日：2003-05-29

申请人： Ernest Knoll ,  Eyal Fayneh

发明人： Ernest Knoll ,  Eyal Fayneh

IPC分类号： G01R23/12 ,  G01R31/02 ,  H03L7/00 ,  H03L7/06 ,  H03L7/089 ,  H03L7/12 ,  H03L7/18

CPC分类号： H03L7/10 ,  H03L7/0893 ,  H03L7/12 ,  H03L7/18

摘要： An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.

摘要翻译： 用于控制锁相环的装置包括用于检测启动条件和绞盘状况中的至少一个的检测器和用于控制电荷泵和锁相环之间的电流的控制器。 如果检测到启动条件，则控制器从连接到锁相环的环路滤波器的控制节点吸收电流。 这反过来导致偏置电压增加，直到锁相环从启动模式转换到正常采集模式。 电流吸收器由虚拟电荷泵提供，并且通过检测PLL禁止状态的结束来确定启动条件。 如果检测到牦牛病情，则连接到锁相环的相位频率检测器的电荷泵控制偏置电压，直到反馈频率变得低于参考频率。 在两种操作模式下控制锁相环的方法可以使用上述装置。

公开(公告)号：US20050044455A1

公开(公告)日：2005-02-24

申请号：US10645660

申请日：2003-08-22

申请人： Eyal Fayneh ,  Ernest Knoll

发明人： Eyal Fayneh ,  Ernest Knoll

IPC分类号： G06F1/04 ,  G06K5/04 ,  G11B5/00 ,  G11B20/20 ,  H03K5/156

CPC分类号： G06F1/04 ,  H03K5/1565

摘要： A control circuit corrects duty-cycle distortion of clock signals accurately and with a fast and continuous response over a wide dynamic range. In one embodiment, the duty-cycle correction circuit includes a self-biased loop that corrects duty-cycle distortions to preferably less than ±1%. The duty-cycle correction circuit also compensates for changes in a supply voltage. These corrections may take place on a continuous basis, not only during a testing period but also during normal operation of the host system driven by the clock signals.

摘要翻译： 控制电路在宽动态范围内精确地和快速连续的响应来校正时钟信号的占空比失真。 在一个实施例中，占空比校正电路包括将占空比失真校正至优选小于±1％的自偏置环路。 占空比校正电路还补偿电源电压的变化。 不仅在测试期间，而且在由时钟信号驱动的主机系统的正常操作期间，这些校正可以连续进行。

公开(公告)号：US06810486B2

公开(公告)日：2004-10-26

申请号：US09818614

申请日：2001-03-28

申请人： Eyal Fayneh ,  Earnest Knoll

发明人： Eyal Fayneh ,  Earnest Knoll

IPC分类号： G06F104

CPC分类号： G06F1/10

摘要： A technique for de-skewing second and third clocks with respect to a first clock includes receiving the first clock and generating a fourth clock from the first and second clocks. A fifth clock and the third clock are generated from the fourth clock, the fifth clock being substantially identical to the third clock. The second clock is then generated from the fifth clock. The fourth clock is generated by a first phase locked loop having the first and second clocks as its inputs and the second clock is generated by a second phase locked loop connected to a clock tree, the second phase locked loop having the fifth clock and the second clock as its inputs.

摘要翻译： 用于相对于第一时钟去偏斜第二和第三时钟的技术包括接收第一时钟并从第一和第二时钟产生第四时钟。 从第四时钟产生第五时钟和第三时钟，第五时钟与第三时钟基本相同。 然后从第五个时钟产生第二个时钟。 所述第四时钟由具有所述第一和第二时钟作为其输入的第一锁相环生成，所述第二时钟由连接到时钟树的第二锁相环产生，所述第二锁相环具有所述第五时钟和所述第二时钟 时钟作为其输入。

公开(公告)号：US06654899B2

公开(公告)日：2003-11-25

申请号：US09818615

申请日：2001-03-28

申请人： Eyal Fayneh ,  Earnest Knoll

发明人： Eyal Fayneh ,  Earnest Knoll

IPC分类号： G06F300

CPC分类号： H03L7/23 ,  G06F1/04

摘要： A tracking bin split technique includes: receiving an externally generated board clock and selectively generating a reference clock in phase with the externally generated board clock at a frequency equal to that of the externally generated board clock multiplied by M, wherein M is an integer equal to or greater than one; receiving the reference clock output by the clock generator and generating an output clock with a phase locked loop in phase with the reference clock and having a frequency which is an integral multiple of that of the reference clock; and receiving the output clock generated by the phase locked loop and generating a feedback clock for the phase locked loop in phase with the output clock and at a frequency equal to that of the output clock divided by 2N, wherein 2N is an even integer equal to or greater than two.

公开(公告)号：US06329882B1

公开(公告)日：2001-12-11

申请号：US09468220

申请日：1999-12-20

申请人： Eyal Fayneh ,  Ernest Knoll

发明人： Eyal Fayneh ,  Ernest Knoll

IPC分类号： H03L7093

CPC分类号： H03L7/0893 ,  H03L2207/06

摘要： A self-biased phase-locked loop circuit includes a phase detector, first and second charge pumps, first and second loop filters, and a voltage-controlled oscillator (VCO). The phase detector is configured to measure a phase offset between two input signals, and to generate pulses corresponding to the phase offset. The first and second charge pumps are configured to provide charge corresponding to the pulses. The first and second loop filters are coupled to outputs of the first and second charge pumps, respectively. The filters operate to provide a control signal responsive to the charge. The VCO is configured to adjust its output frequency in response to the control signal. The second loop filter capacitor considerably improves the output clock jitter.

摘要翻译： 自偏置锁相环电路包括相位检测器，第一和第二电荷泵，第一和第二环路滤波器以及压控振荡器（VCO）。 相位检测器被配置为测量两个输入信号之间的相位偏移，并且产生对应于相位偏移的脉冲。 第一和第二电荷泵配置成提供对应于脉冲的电荷。 第一和第二环路滤波器分别耦合到第一和第二电荷泵的输出端。 滤波器操作以响应于电荷提供控制信号。 VCO被配置为响应于控制信号调整其输出频率。 第二个环路滤波电容大大提高了输出时钟抖动。

公开(公告)号：US06233200B1

公开(公告)日：2001-05-15

申请号：US09465220

申请日：1999-12-15

申请人： Ernest Knoll ,  Eyal Fayneh

发明人： Ernest Knoll ,  Eyal Fayneh

IPC分类号： G11C800

CPC分类号： G06F1/10 ,  H03L7/095

摘要： A clock distribution network includes a phase-locked loop (PLL), clock buffers, an enabling circuit, and a distribution inhibit circuit. The PLL is configured to generate a clock signal and a lock detect signal. The clock buffers are adapted to receive the clock signal from the PLL. The buffers have outputs that can be connected to clock loads. The enabling circuit enables selected buffers to drive the clock loads. The distribution inhibit circuit selectively produces the enable signal to inhibit distribution of the clock signal responsive to the lock detect signal.

摘要翻译： 时钟分配网络包括锁相环（PLL），时钟缓冲器，使能电路和分配禁止电路。 PLL被配置为产生时钟信号和锁定检测信号。 时钟缓冲器适于从PLL接收时钟信号。 缓冲器具有可连接到时钟负载的输出。 启用电路使选定的缓冲区能够驱动时钟负载。 分配禁止电路响应于锁定检测信号选择性地产生使能信号以禁止时钟信号的分配。