公开(公告)号：US6127700A

公开(公告)日：2000-10-03

申请号：US527399

申请日：1995-09-12

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/76 ,  H01L29/94 ,  H01L1/062

CPC classification number: H01L29/66659 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/1045

Abstract: An insulated-gate field-effect transistor utilizes local threshold-adjust doping to control the voltage at which the transistor turns on. The local threshold-adjust doping is present along part, but not all, of the lateral extent of the channel. In the transistor structure, a channel zone laterally separates a pair of source/drain zones. The channel zone is formed with a main channel portion and a more heavily doped threshold channel portion that contains the local threshold-adjust doping. Gate dielectric material vertically separates the channel zone from an overlying gate electrode. The transistor is a long device in that the gate electrode is longer, preferably at least 50% longer, than the gate electrode of a minimum-sized transistor whose gate length is approximately the minimum feature size. The long-gate transistor is suitable for use in analog and high-voltage digital portions of a VLSI circuit.

Abstract translation: 绝缘栅场效应晶体管利用局部阈值调整掺杂来控制晶体管导通的电压。 局部阈值调整掺杂沿着通道的横向范围的部分而不是全部存在。 在晶体管结构中，沟道区横向分离一对源极/漏极区。 通道区形成有主通道部分和更高掺杂的阈值通道部分，其包含局部阈值调整掺杂。 栅介质材料将沟道区与上覆栅电极垂直分开。 晶体管是一种长的器件，其栅极长度比栅极长度近似为最小特征尺寸的最小尺寸晶体管的栅极电极长，优选至少50％更长。 长栅极晶体管适用于VLSI电路的模拟和高压数字部分。

公开(公告)号：US5701023A

公开(公告)日：1997-12-23

申请号：US285581

申请日：1994-08-03

Applicant: Constantin Bulucea ,  Richard A. Blanchard

Inventor： Constantin Bulucea ,  Richard A. Blanchard

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/74 ,  H01L29/76

CPC classification number: H01L29/7813 ,  H01L29/7802 ,  H01L29/7808 ,  H01L29/0626 ,  H01L29/1095 ,  Y10S438/965

Abstract: An insulated gate semiconductor device contains a common drain and a plurality of cells, each having a body region and a source. In each cell, the body region contains a channel region extending between the common drain and the source. The body region further includes a special portion spaced apart from the channel region, more heavily doped than the portion of the body region below the source, extending no more than an electrically insignificant amount below the source, and not extending significantly deeper below the upper semiconductor surface than the portion of the body region underlying the source. The special portion of each body region provides improved ruggedness under drain avalanche conditions. The special portion of each body region normally reaches a peak net dopant concentration below the upper semiconductor surface. Instead of, or in addition to, having the special portion of each body region be subsurface-peaked, the portion of each body region below the source can extend deeper below the upper semiconductor surface than the portion of the body region underlying the special portion.

Abstract translation: 绝缘栅半导体器件包含共同漏极和多个单元，每个单元具有体区和源极。 在每个单元中，主体区域包含在公共漏极和源极之间延伸的沟道区域。 主体区域还包括与沟道区间隔开的特别部分，比源极下方的主体区域的部分更重的掺杂，在源极之下不超过电位不大的量，并且在上半导体之下不会显着更深地延伸 表面比源的身体区域的部分。 每个身体区域的特殊部分在排水雪崩条件下提供改善的耐久性。 每个体区的特殊部分通常达到低于上半导体表面的峰值净掺杂浓度。 代替或除了使每个体区的特殊部分具有次表面峰值之外，源极下方的每个体区域的部分可以比在特定部分下方的身体区域的部分更深地延伸到上半导体表面之下。

公开(公告)号：US5298442A

公开(公告)日：1994-03-29

申请号：US762103

申请日：1991-09-18

Applicant: Constantin Bulucea ,  Rebecca Rossen

Inventor： Constantin Bulucea ,  Rebecca Rossen

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L21/335

CPC classification number: H01L29/4232 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7813 ,  H01L29/402 ,  H01L29/4238 ,  Y10S148/126

Abstract: Power MOSFET apparatus, and method for its production, that suppresses voltage breakdown near the gate, using a polygon-shaped trench in which the gate is positioned, using a shaped deep body junction that partly lies below the trench bottom, and using special procedures for growth of gate oxide at various trench corners.

Abstract translation: 功率MOSFET器件及其制造方法，使用位于沟槽底部下方的成形深体结，使用位于栅极的多边形沟槽来抑制栅极附近的电压击穿，并使用特殊程序 栅极氧化物在各种沟角处的生长。

公开(公告)号：US5072266A

公开(公告)日：1991-12-10

申请号：US290546

申请日：1988-12-27

Applicant: Constantin Bulucea ,  Rebecca Rossen

Inventor： Constantin Bulucea ,  Rebecca Rossen

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/4232 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7813 ,  H01L29/402 ,  H01L29/4238 ,  Y10S148/126

Abstract: Power MOSFET apparatus, and method for its production, that suppresses voltage breakdown near the gate, using a polygon-shaped trench in which the gate is positioned in order to suppress oxide dielectric breakdown, using a shaped deep body junction that partly lies below the trench bottom to force voltage breakdown away from the trench surfaces and into the bulk of the semiconductor material, and using special procedures for growth of gate oxide at various trench corners.

Abstract translation: 功率MOSFET器件及其制造方法，其使用位于栅极的多边形沟槽来抑制栅极附近的电压击穿，以便使用部分位于沟槽下方的成形深体结，以抑制氧化物介电击穿 底部以迫使电压从沟槽表面远离并进入半导体材料的主体，并且使用用于在各种沟槽角处生长栅极氧化物的特殊程序。

公开(公告)号：US08304320B2

公开(公告)日：2012-11-06

申请号：US13100192

申请日：2011-05-03

Applicant: Sandeep R. Bahl ,  William D. French ,  Constantin Bulucea

Inventor： Sandeep R. Bahl ,  William D. French ,  Constantin Bulucea

IPC: H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/7835 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/82285 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/6659 ,  H01L29/66659

Abstract: An insulated-gate field-effect transistor (100) provided along an upper surface of a semiconductor body contains a pair of source/drain zones (240 and 242) laterally separated by a channel zone (244). A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. Each source/drain zone includes a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E) laterally continuous with the main portion and extending laterally under the gate electrode. The lateral extensions, which terminate the channel zone along the upper semiconductor surface, are respectively largely defined by a pair of semiconductor dopants of different atomic weights. With the transistor being an asymmetric device, the source/drain zones constitute a source and a drain. The lateral extension of the source is then more lightly doped than, and defined with dopant of higher atomic weight, than the lateral extension of the drain.

Abstract translation: 沿着半导体主体的上表面设置的绝缘栅场效应晶体管（100）包含由沟道区（244）横向隔开的一对源极/漏极区（240和242）。 栅电极（262）覆盖沟道区上方的栅介电层（260）。 每个源极/漏极区域包括与主要部分横向连续并在栅电极下方横向延伸的主要部分（240M或242M）和更轻掺杂的侧向延伸部（240E或242E）。 沿着上半导体表面终止沟道区的横向延伸部分分别由不同原子量的一对半导体掺杂剂限定。 在晶体管是非对称器件的情况下，源极/漏极区域构成源极和漏极。 源极的横向延伸比起漏极的横向延伸稍微掺杂，并且由原子量较高的掺杂剂限定。

公开(公告)号：US20120139013A1

公开(公告)日：2012-06-07

申请号：US12959736

申请日：2010-12-03

Applicant: Sandeep Bahl ,  Constantin Bulucea

Inventor： Sandeep Bahl ,  Constantin Bulucea

IPC: H01L29/808 ,  H01L21/337

CPC classification number: H01L29/7722 ,  H01L27/085

Abstract: A static induction transistor comprising: a region of semiconductor material having a first conductivity type; at least two spaced-apart gate regions formed in the region of semiconductor material, the gate regions having a second conductivity type that is opposite to the first conductivity type; at least one source region having the first conductivity type formed in the region of semiconductor material between the spaced-apart gate regions; a drain region having the first conductivity type formed in the region of semiconductor and spaced-apart from the source region to define a channel region therebetween; and a dielectric carrier separation layer formed at the periphery of the gate regions.

Abstract translation: 一种静电感应晶体管，包括：具有第一导电类型的半导体材料区域; 形成在所述半导体材料区域中的至少两个间隔开的栅极区域，所述栅极区域具有与所述第一导电类型相反的第二导电类型; 在所述间隔开的栅极区域之间的半导体材料的区域中形成具有第一导电类型的至少一个源极区域; 具有第一导电类型的漏极区，形成在半导体区域中并与源极区间隔开以在其间限定沟道区; 以及形成在栅极区域的周边的介电载体分离层。

公开(公告)号：US08163619B2

公开(公告)日：2012-04-24

申请号：US12382967

申请日：2009-03-27

Applicant: Jeng-Jiun Yang ,  Constantin Bulucea ,  Sandeep R. Bahl

Inventor： Jeng-Jiun Yang ,  Constantin Bulucea ,  Sandeep R. Bahl

IPC: H01L21/336

CPC classification number: H01L29/7835 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66659

Abstract: An asymmetric insulated-gate field effect transistor (100U or 102U) is provided along an upper surface of a semiconductor body so as to have first and second source/drain zones (240 and 242 or 280 and 282) laterally separated by a channel zone (244 or 284) of the transistor's body material. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A pocket portion (250 or 290) of the body material more heavily doped than laterally adjacent material of the body material extends along largely only the first of the S/D zones and into the channel zone. The vertical dopant profile of the pocket portion is tailored to reach a plurality of local maxima at respective locations (PH-1-PH-3-NH-3) spaced apart from one another. This typically enables the transistor to have reduced current leakage.

Abstract translation: 沿着半导体主体的上表面设置非对称绝缘栅场效应晶体管（100U或102U），以便具有由沟道区横向隔开的第一和第二源/漏区（240和242或280和282） 244或284）晶体管的主体材料。 栅电极（262或302）覆盖在沟道区上方的栅介电层（260或300）。 比主体材料的横向相邻材料更重掺杂的主体材料的口袋部分（250或290）在很大程度上仅延伸到第一个S / D区域并进入通道区域。 口袋部分的垂直掺杂剂轮廓被调整为在彼此间隔开的相应位置（PH-1-PH-3-NH-3）处达到多个局部最大值。 这通常使得晶体管具有减小的电流泄漏。

公开(公告)号：US07863681B1

公开(公告)日：2011-01-04

申请号：US12545024

申请日：2009-08-20

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L27/088

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262). The combination of the hypoabrupt vertical dopant profile below the first-mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second-mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.

Abstract translation: 绝缘栅场效应晶体管（100,100V，140,150,150V，160,170,170V，180,180V，190,210,210W，220,220U，220V，220W，380或480）具有 低于其源极/漏极区（104或264）的垂直掺杂剂分布，用于减小源极/漏极区与邻接体材料（108或268）之间的pn结的寄生电容。 特别地，限定主体材料的导电类型的半导体掺杂剂的浓度在从该源极/漏极区向下移动到下面的主体材料位置时不小于10倍深度的上方增加至少10倍 半导体表面比该源/漏区。 主体材料优选地包括沿着另一个源极/漏极区（102或262）设置的更重掺杂的凹穴部分（120或280）。 通常用作漏极的第一提及的源极/漏极区下方的低破坏垂直掺杂物分布以及通常用作源的第二次提供的源极/漏极区的凹穴部分的组合使得所得的不对称晶体管能够 特别适用于高速模拟应用。

公开(公告)号：US07838369B2

公开(公告)日：2010-11-23

申请号：US11981355

申请日：2007-10-31

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L27/088

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/1203

Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) is fabricated so as to have a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material is preferably provided with a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262). The combination of the hypoabrupt vertical dopant profile below the first-mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second-mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.

Abstract translation: 制造绝缘栅场效应晶体管（100,100V，140,150,150V，160,170,170V，180,180V，190,210,210W，220,220U，220V，220W，380或480） 以便具有低于其源极/漏极区的一个（104或264）的低破坏垂直掺杂剂轮廓，用于减小沿着该源极/漏极区与邻接主体材料（108或268）之间的pn结的寄生电容。 特别地，限定主体材料的导电类型的半导体掺杂剂的浓度在从该源极/漏极区向下移动到下面的物体 - 物质位置之前至少增加10倍，不超过上部的10倍 半导体表面比该源/漏区。 主体材料优选地设置有沿着另一个源极/漏极区（102或262）设置的更加重掺杂的凹穴部分（120或280）。 通常用作漏极的第一提及的源极/漏极区下方的低破坏垂直掺杂物分布以及通常用作源的第二次提供的源极/漏极区的凹穴部分的组合使得所得的不对称晶体管能够 特别适用于高速模拟应用。

公开(公告)号：US20100244152A1

公开(公告)日：2010-09-30

申请号：US12382976

申请日：2009-03-27

Applicant: Sandeep R. Bahl ,  Constantin Bulucea ,  William D. French

Inventor： Sandeep R. Bahl ,  Constantin Bulucea ,  William D. French

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/26513 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: An extended-drain insulated-gate field-effect transistor (104 or 106) contains first and second source/drain zones 324 and 184B or 364 and 186B) laterally separated by a channel (322 or 362) zone constituted by part of a first well region (184A or 186A). A gate dielectric layer (344 or 384) overlies the channel zone. A gate electrode (346 or 386) overlies the gate dielectric layer above the channel zone. The first source/drain zone is normally the source. The second S/D zone, normally the drain, is constituted with a second well region (184B or 186B). A well-separating portion 186A or 186B/212U) of the semiconductor body extends between the well regions and is more lightly doped than each well region. The configuration of the well regions cause the maximum electric field in the IGFET's portion of the semiconductor body to occur well below the upper semiconductor surface, typically at or close to where the well regions are closest to each other. The IGFET's operating characteristics are stable with operational time.

Abstract translation: 扩展漏极绝缘栅场效应晶体管（104或106）包含由第一阱的一部分构成的沟道（322或362）区域横向隔开的第一和第二源/漏区324和184B或364和186B， 区域（184A或186A）。 栅极电介质层（344或384）覆盖在沟道区上。 栅电极（346或386）覆盖沟道区上方的栅介质层。 第一个源/漏区通常是源。 第二S / D区（通常为漏极）由第二阱区（184B或186B）构成。 半导体本体的阱分离部分186A或186B / 212U）在阱区之间延伸，并且比每个阱区域轻掺杂。 阱区域的配置导致半导体本体的IGFET的部分中的最大电场远低于上半导体表面，通常处于或接近阱区彼此最接近的位置。 IGFET的运行特性在运行时间稳定。