公开(公告)号：US20150206844A1

公开(公告)日：2015-07-23

申请号：US14159944

申请日：2014-01-21

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc.

Inventor： Daniel Thanh Khae Pham ,  Xiuyu Cai ,  Bala Subramanian Pranatharthi Haran ,  Charan Veera Venkata Satya Surisetty ,  Jin Wook Lee ,  Shom Ponoth ,  David V. Horak

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L27/06

CPC classification number: H01L21/76816 ,  H01L21/28247 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods of forming integrated circuits are provided. An integrated circuit includes a gate electrode structure overlying a base substrate. The gate electrode structure includes a gate electrode, with a cap disposed over the gate electrode and sidewall spacers disposed adjacent to sidewalls of the gate electrode structure. A source and drain region are formed in the base substrate aligned with the gate electrode structure. A first dielectric layer is disposed adjacent to the sidewall spacers. The sidewall spacers and the cap have recessed surfaces below a top surface of the first dielectric layer, and a protecting layer is disposed over the recessed surfaces. A second dielectric layer is disposed over the first dielectric layer and the protecting layer. Electrical interconnects are disposed through the first dielectric layer and the second dielectric layer, and the electrical interconnects are in electrical communication with the respective source and drain regions.

Abstract translation: 提供了形成集成电路的集成电路和方法。 集成电路包括覆盖基底的栅电极结构。 栅极电极结构包括栅电极，栅极设置在栅电极上，侧壁间隔件邻近栅电极结构的侧壁设置。 源极和漏极区域形成在与栅电极结构对准的基底衬底中。 第一电介质层设置成与侧壁间隔物相邻。 侧壁间隔件和盖在第一电介质层的顶表面下方具有凹陷表面，并且保护层设置在凹入表面之上。 第二电介质层设置在第一电介质层和保护层之上。 电互连通过第一介电层和第二介电层设置，并且电互连与相应的源区和漏区电连通。

公开(公告)号：US20150206754A1

公开(公告)日：2015-07-23

申请号：US14161724

申请日：2014-01-23

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： David V. Horak ,  Shom S. Ponoth ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L21/28 ,  H01L29/423

CPC classification number: H01L29/0653 ,  H01L21/28008 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.

Abstract translation: 形成半导体结构的方法包括在半导体衬底上形成具有第一导电材料的栅极结构，在第一导电材料的相对侧上的栅极间隔物和围绕栅极间隔物的第一层间电介质（ILD）层和第一导电 材料。 第一导电材料的上部是凹进的。 栅极间隔物凹进直到栅极间隔物的高度小于栅极结构的高度。 隔离衬垫沉积在栅极间隔物和第一导电材料上方。 去除隔离衬垫的一部分，使得第一导电材料的顶表面露出。 第二导电材料沉积在形成在第一导电材料和栅极间隔物上方的接触孔中以形成栅极接触。

公开(公告)号：US08937359B2

公开(公告)日：2015-01-20

申请号：US13894513

申请日：2013-05-15

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Shom Ponoth ,  David V. Horak ,  Balasubramanian Pranatharthiharan

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/66666

Abstract: Embodiments of the invention provide approaches for forming gate and source/drain (S/D) contacts. Specifically, the semiconductor device includes a gate transistor formed over a substrate, a S/D contact formed over a trench-silicide (TS) layer and positioned adjacent the gate transistor, and a gate contact formed over the gate transistor, wherein at least a portion of the gate contact is aligned over the TS layer. This structure enables contact with the TS layer, thereby decreasing the distance between the gate contact and the source/drain, which is desirable for ultra-area-scaling.

Abstract translation: 本发明的实施例提供了用于形成栅极和源极/漏极（S / D）触点的方法。 具体地，半导体器件包括形成在衬底上的栅极晶体管，形成在沟槽硅化物（TS）层上并且邻近栅极晶体管定位的S / D接触，以及形成在栅极晶体管上的栅极接触，其中至少一个 栅极触点的一部分在TS层上对齐。 这种结构使得能够与TS层接触，从而减小栅极接触和源极/漏极之间的距离，这对于超区域缩放是期望的。