公开(公告)号：US20190139823A1

公开(公告)日：2019-05-09

申请号：US15804006

申请日：2017-11-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hsueh-Chung Chen ,  Jason E. Stephens ,  Lars W. Liebmann ,  Guillaume Bouche

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/3213

Abstract: One illustrative method disclosed herein may include forming first and second via openings and forming conductive material for first and second conductive vias across substantially an entirety of an upper surface of a layer of insulating material and in the via openings. A patterned line etch mask layer is then formed above the conductive material, the etch mask having a first feature corresponding to a first conductive line and a second feature corresponding to a second conductive line, and performing at least one etching process to define the first and second conductive lines that are arranged in a tip-to-tip configuration. In this example, a first edge of the first conductive via is substantially aligned with a first end of the first conductive line and a second edge of the second conductive via is substantially aligned with a second end of the second conductive line.

公开(公告)号：US10204994B2

公开(公告)日：2019-02-12

申请号：US15477565

申请日：2017-04-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Andre P. Labonte ,  Lars W. Liebmann ,  Nigel G. Cave ,  Mark V. Raymond ,  Guillaume Bouche ,  David E. Brown

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213

Abstract: One illustrative device disclosed herein includes, among other things, a stepped conductive source/drain structure with a first recess defined therein and a stepped final gate structure with a second recess defined therein, wherein, when viewed from above, the second recess is axially and laterally offset from the first recess. In this example, the device also includes a layer of insulating material positioned above the stepped conductive source/drain structure and the stepped final gate structure, a conductive gate (CB) contact that is conductively coupled to the stepped final gate structure and a conductive source/drain (CA) contact that is conductively coupled to the stepped conductive source/drain structure.

公开(公告)号：US10128352B2

公开(公告)日：2018-11-13

申请号：US15432372

申请日：2017-02-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L23/535 ,  H01L29/66 ,  H01L21/768 ,  H01L21/027 ,  H01L27/11 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.

公开(公告)号：US09735054B2

公开(公告)日：2017-08-15

申请号：US15175776

申请日：2016-06-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L21/027 ,  H01L29/66 ,  H01L23/535 ,  H01L27/11 ,  H01L21/311

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

公开(公告)号：US20170170070A1

公开(公告)日：2017-06-15

申请号：US15443523

申请日：2017-02-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L29/66

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

公开(公告)号：US09627257B2

公开(公告)日：2017-04-18

申请号：US15175835

申请日：2016-06-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L29/66 ,  H01L27/11 ,  H01L23/535

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

公开(公告)号：US20170047254A1

公开(公告)日：2017-02-16

申请号：US15175835

申请日：2016-06-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L27/11 ,  H01L23/535 ,  H01L29/66

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

公开(公告)号：US20170047252A1

公开(公告)日：2017-02-16

申请号：US15175776

申请日：2016-06-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

Abstract translation: 用于形成栅极结合的方法包括：在栅极结构上打开盖层和凹入栅极间隔物以暴露栅极导体; 在所述栅极间隔物上形成内部间隔物; 蚀刻与栅极结构的侧面相邻的接触开口，直到栅极结构下面的衬底; 以及在栅极结构的侧面上形成沟槽接触。 层间电介质（ILD）沉积在栅极导体上并且沟槽接触并在栅极结构上方。 ILD被打开以暴露栅极结构和栅极导体的一侧上的沟槽接触。 第二导电材料在一侧提供自对准接触，直到沟槽接触，并且形成到栅极导体的栅极接触，以及在栅极导体和自对准的有源区域之间的ILD内的水平连接 联系。

公开(公告)号：US09397049B1

公开(公告)日：2016-07-19

申请号：US14822654

申请日：2015-08-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L23/535 ,  H01L21/768 ,  H01L29/66 ,  H01L29/40 ,  H01L27/11 ,  H01L21/027

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

Abstract translation: 用于形成栅极结合的方法包括：在栅极结构上打开盖层和凹入栅极间隔物以暴露栅极导体; 在所述栅极间隔物上形成内部间隔物; 蚀刻与栅极结构的侧面相邻的接触开口，直到栅极结构下面的衬底; 以及在栅极结构的侧面上形成沟槽接触。 层间电介质（ILD）沉积在栅极导体上并且沟槽接触并在栅极结构上方。 ILD被打开以暴露栅极结构和栅极导体的一侧上的沟槽接触。 第二导电材料在一侧提供自对准接触，直到沟槽接触，并且形成到栅极导体的栅极接触，以及在栅极导体和自对准的有源区域之间的ILD内的水平连接 联系。

公开(公告)号：US09335626B2

公开(公告)日：2016-05-10

申请号：US13960873

申请日：2013-08-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Neal V. Lafferty ,  Lars W. Liebmann

IPC: G06F17/50 ,  G03F1/70

CPC classification number: G03F1/70

Abstract: A design level compatible with a sidewall image transfer process employs an alternating grid of mandrel-type line tracks and non-mandrel-type line tracks. Target structure design shapes are formed such that all vertices of the target structure design shapes are on the grid. The target structure design shapes are classified as mandrel-type design shapes and non-mandrel-type design shapes depending on the track type of the overlapping line tracks for lengthwise portions. All mandrel-type line tracks and straps of the mandrel-type design shapes less lateral strap regions of the non-mandrel-type design shapes collectively form mandrel design shapes, which can be employed to generate a first lithographic mask. Sidewall design shapes are generated from the mandrel design shapes. Blocking shapes for a second lithographic mask can be generated by selecting all areas that are not included in the target structure design shapes or the sidewall design shapes.

Abstract translation: 与侧壁图像转印过程兼容的设计级别采用心轴式线轨道和非心轴型线轨道的交替网格。 形成目标结构设计形状，使得目标结构设计形状的所有顶点都在网格上。 目标结构设计形状根据纵向部分的重叠线轨道的轨道类型分为心轴型设计形状和非心轴型设计形状。 心轴型设计的所有心轴型线轨和带形形状较少的非心轴型设计形状的侧向带区域共同形成心轴设计形状，其可用于产生第一平版印刷掩模。 侧壁设计形状由心轴设计形状产生。 可以通过选择不包括在目标结构设计形状或侧壁设计形状中的所有区域来产生用于第二光刻掩模的阻挡形状。