公开(公告)号：US09465907B2

公开(公告)日：2016-10-11

申请号：US14341092

申请日：2014-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ahmed Hassan ,  Nader Magdy Hindawy ,  Vikrant Chauhan ,  Jason Eugene Stephens ,  David Pritchard ,  Abbas Guvenilir ,  David E. Brown ,  Terry J. Bordelon, Jr.

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G06F17/5068 ,  G06F17/5072

Abstract: One illustrative method disclosed herein involves, among other things, decomposing an initial circuit layout into first and second mask patterns, for the first mask pattern, identifying a first four-polygon pattern in the first mask pattern that violates a multi-polygon constraint rule, wherein the first four-polygon pattern comprises four polygons positioned side-by-side in the first mask pattern, and recoloring one or two of the polygons in the first four-polygon pattern in the first mask pattern to the second mask pattern to eliminate the first four-polygon pattern from the first mask pattern without introducing any design rule violations in the initial circuit layout.

Abstract translation: 本文公开的一种说明性方法涉及对于第一掩模图案将初始电路布局分解为第一和第二掩模图案，识别违反多边形约束规则的第一掩模图案中的第一四边形图案， 其中所述第一四面体图案包括在所述第一掩模图案中并排定位的四个多边形，以及将所述第一掩模图案中的所述第一四面体图案中的一个或两个多边形重新染色到所述第二掩模图案以消除 在第一掩模图案中的第一四面多边形图案，而不会在初始电路布局中引入任何设计规则违规。

公开(公告)号：US20160026748A1

公开(公告)日：2016-01-28

申请号：US14341092

申请日：2014-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ahmed Hassan ,  Nader Magdy Hindawy ,  Vikrant Chauhan ,  Jason Eugene Stephens ,  David Pritchard ,  Abbas Guvenilir ,  David E. Brown ,  Terry J. Bordelon, Jr.

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G06F17/5068 ,  G06F17/5072

Abstract: One illustrative method disclosed herein involves, among other things, decomposing an initial circuit layout into first and second mask patterns, for the first mask pattern, identifying a first four-polygon pattern in the first mask pattern that violates a multi-polygon constraint rule, wherein the first four-polygon pattern comprises four polygons positioned side-by-side in the first mask pattern, and recoloring one or two of the polygons in the first four-polygon pattern in the first mask pattern to the second mask pattern to eliminate the first four-polygon pattern from the first mask pattern without introducing any design rule violations in the initial circuit layout.

Abstract translation: 本文公开的一种说明性方法涉及对于第一掩模图案，将初始电路布局分解为第一和第二掩模图案，识别违反多边形约束规则的第一掩模图案中的第一四边形图案， 其中所述第一四面体图案包括在所述第一掩模图案中并排定位的四个多边形，以及将所述第一掩模图案中的所述第一四面体图案中的一个或两个多边形重新染色到所述第二掩模图案以消除 在第一掩模图案中的第一四面多边形图案，而不会在初始电路布局中引入任何设计规则违规。

公开(公告)号：US10204994B2

公开(公告)日：2019-02-12

申请号：US15477565

申请日：2017-04-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Andre P. Labonte ,  Lars W. Liebmann ,  Nigel G. Cave ,  Mark V. Raymond ,  Guillaume Bouche ,  David E. Brown

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213

Abstract: One illustrative device disclosed herein includes, among other things, a stepped conductive source/drain structure with a first recess defined therein and a stepped final gate structure with a second recess defined therein, wherein, when viewed from above, the second recess is axially and laterally offset from the first recess. In this example, the device also includes a layer of insulating material positioned above the stepped conductive source/drain structure and the stepped final gate structure, a conductive gate (CB) contact that is conductively coupled to the stepped final gate structure and a conductive source/drain (CA) contact that is conductively coupled to the stepped conductive source/drain structure.

公开(公告)号：US20180286956A1

公开(公告)日：2018-10-04

申请号：US15477565

申请日：2017-04-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Andre P. Labonte ,  Lars W. Liebmann ,  Nigel G. Cave ,  Mark V. Raymond ,  Guillaume Bouche ,  David E. Brown

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213

CPC classification number: H01L29/41775 ,  H01L21/32139 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/66545

Abstract: One illustrative device disclosed herein includes, among other things, a stepped conductive source/drain structure with a first recess defined therein and a stepped final gate structure with a second recess defined therein, wherein, when viewed from above, the second recess is axially and laterally offset from the first recess. In this example, the device also includes a layer of insulating material positioned above the stepped conductive source/drain structure and the stepped final gate structure, a conductive gate (CB) contact that is conductively coupled to the stepped final gate structure and a conductive source/drain (CA) contact that is conductively coupled to the stepped conductive source/drain structure.