公开(公告)号：US10115738B2

公开(公告)日：2018-10-30

申请号：US15354205

申请日：2016-11-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Min-Hwa Chi

IPC: H01L29/10 ,  H01L27/12 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/49

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to self-aligned back-plane and well contacts for a fully depleted silicon on insulator device and methods of manufacture. The structure includes a back-plane, a p-well and an n-well formed within a bulk substrate; a contact extending from each of the back-plane, the p-well and the n-well; a gate structure formed above the back-plane, the p-well and the n-well; and an insulating spacer isolating the contact of the back-plane from the gate structure.

公开(公告)号：US09842927B1

公开(公告)日：2017-12-12

申请号：US15248367

申请日：2016-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred J Eller ,  Min-Hwa Chi ,  Jerome J. B. Ciavatti

IPC: H01L29/49 ,  H01L29/43 ,  H01L27/092 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/783 ,  H01L27/1104 ,  H01L29/41775 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/66795

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate structure between a pair of gate spacers within a dielectric layer and substantially surrounding a fin, wherein the gate structure is disposed adjacent to a channel region within the fin; and a source/drain contact extending within the dielectric layer to a source/drain region within a fin, the source/drain contact being separated from the gate structure by at least one gate spacer in the pair of gate spacers, wherein the channel region and the source/drain region provide electrical connection between the gate structure and the source/drain contact.

公开(公告)号：US09831175B2

公开(公告)日：2017-11-28

申请号：US15489404

申请日：2017-04-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Suraj Kumar Patil ,  Min-Hwa Chi

IPC: H01L21/8238 ,  H01L23/525 ,  H01L45/00 ,  H01L27/112 ,  H01L23/62 ,  H01L23/535

CPC classification number: H01L23/5256 ,  H01L23/535 ,  H01L23/62 ,  H01L27/11206 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146

Abstract: Methods, apparatus, and systems for fabricating and using a semiconductor device comprising a first conductive element; a second conductive element; and an e-fuse comprising a first region comprising a conductive oxide of a first metal; and a second region comprising a second metal, wherein an oxide of the second metal is resistive; wherein the e-fuse is electrically connected to both the first conductive element and the second conductive element.

公开(公告)号：US20170221823A1

公开(公告)日：2017-08-03

申请号：US15489404

申请日：2017-04-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Suraj Kumar Patil ,  Min-Hwa Chi

IPC: H01L23/525 ,  H01L23/535 ,  H01L23/62 ,  H01L45/00 ,  H01L27/112

CPC classification number: H01L23/5256 ,  H01L23/535 ,  H01L23/62 ,  H01L27/11206 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146

Abstract: Methods, apparatus, and systems for fabricating and using a semiconductor device comprising a first conductive element; a second conductive element; and an e-fuse comprising a first region comprising a conductive oxide of a first metal; and a second region comprising a second metal, wherein an oxide of the second metal is resistive; wherein the e-fuse is electrically connected to both the first conductive element and the second conductive element.

公开(公告)号：US20170141214A1

公开(公告)日：2017-05-18

申请号：US15343821

申请日：2016-11-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Min-Hwa Chi ,  Jinping Liu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L21/306

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/785

Abstract: At least one method, apparatus and system disclosed herein fin field effect transistor (finFET) comprising a tall fin having a plurality of epitaxial regions. A first fin of a transistor is formed. The first fin comprising a first portion comprising silicon, a second portion comprising silicon germanium and a third portion comprising silicon. A gate structure above the third portion is formed. An etching process is performed for removing the silicon germanium of the second portion that is not below the gate structure. A first epitaxy region is formed above the first portion. A second epitaxy region is formed vertically aligned with the first epitaxy region and above the second region.

公开(公告)号：US09653583B1

公开(公告)日：2017-05-16

申请号：US15226165

申请日：2016-08-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Haiting Wang ,  Hongliang Shen ,  Zhenyu Hu ,  Min-Hwa Chi

IPC: H01L21/8238 ,  H01L21/66 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L21/3105

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823878 ,  H01L29/66545

Abstract: One illustrative method disclosed herein includes, among other things, forming a first gate structure above a fin, forming epi semiconductor material on the fin, performing at least one first etching process through a patterned sacrificial layer of material to remove at least a gate cap layer and sacrificial gate materials of the first gate structure so as to define a first isolation cavity that exposes the fin while leaving the second gate structure intact, performing at least one second etching process through the first isolation cavity to remove at least a portion of a vertical height of the fin and thereby form a first isolation trench, removing the patterned sacrificial layer of material, and forming a layer of insulating material above the epi semiconductor material and in the first isolation trench and in the first isolation cavity.