公开(公告)号：US09659862B1

公开(公告)日：2017-05-23

申请号：US14936582

申请日：2015-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj Kumar Patil ,  Min-Hwa Chi

IPC: H01L29/02 ,  H01L47/00 ,  H01L23/525

CPC classification number: H01L23/5256 ,  H01L23/535 ,  H01L23/62 ,  H01L27/11206 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146

Abstract: Methods, apparatus, and systems for fabricating and using a semiconductor device comprising a first conductive element; a second conductive element; and an e-fuse comprising a first region comprising a conductive oxide of a first metal; and a second region comprising a second metal, wherein an oxide of the second metal is resistive; wherein the e-fuse is electrically connected to both the first conductive element and the second conductive element.

公开(公告)号：US10354928B2

公开(公告)日：2019-07-16

申请号：US16038977

申请日：2018-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj Kumar Patil ,  Katsunori Onishi ,  Pei Liu ,  Chih-Chiang Chang

IPC: H01L21/82 ,  H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/49

Abstract: A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.

公开(公告)号：US10056303B1

公开(公告)日：2018-08-21

申请号：US15494119

申请日：2017-04-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj Kumar Patil ,  Katsunori Onishi ,  Pei Liu ,  Chih-Chiang Chang

IPC: H01L21/82 ,  H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/4966

Abstract: A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.

公开(公告)号：US09831175B2

公开(公告)日：2017-11-28

申请号：US15489404

申请日：2017-04-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Suraj Kumar Patil ,  Min-Hwa Chi

IPC: H01L21/8238 ,  H01L23/525 ,  H01L45/00 ,  H01L27/112 ,  H01L23/62 ,  H01L23/535

CPC classification number: H01L23/5256 ,  H01L23/535 ,  H01L23/62 ,  H01L27/11206 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146

Abstract: Methods, apparatus, and systems for fabricating and using a semiconductor device comprising a first conductive element; a second conductive element; and an e-fuse comprising a first region comprising a conductive oxide of a first metal; and a second region comprising a second metal, wherein an oxide of the second metal is resistive; wherein the e-fuse is electrically connected to both the first conductive element and the second conductive element.

公开(公告)号：US20170221823A1

公开(公告)日：2017-08-03

申请号：US15489404

申请日：2017-04-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Suraj Kumar Patil ,  Min-Hwa Chi

IPC: H01L23/525 ,  H01L23/535 ,  H01L23/62 ,  H01L45/00 ,  H01L27/112

CPC classification number: H01L23/5256 ,  H01L23/535 ,  H01L23/62 ,  H01L27/11206 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146

Abstract: Methods, apparatus, and systems for fabricating and using a semiconductor device comprising a first conductive element; a second conductive element; and an e-fuse comprising a first region comprising a conductive oxide of a first metal; and a second region comprising a second metal, wherein an oxide of the second metal is resistive; wherein the e-fuse is electrically connected to both the first conductive element and the second conductive element.

公开(公告)号：US09754843B1

公开(公告)日：2017-09-05

申请号：US15205535

申请日：2016-07-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj Kumar Patil ,  Ajey P. Jacob

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/115 ,  H01L29/788 ,  H01L27/092 ,  H01L29/49 ,  H01L21/302 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L21/823885 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include forming first trenches in a Si, Ge, III-V, or SixGe1-x substrate; forming a conformal SiN, SiOxCyNz layer over side and bottom surfaces of the first trenches; filling the first trenches with SiOx; forming a first mask over portions of the Si, Ge, III-V, or SixGe1-x substrate; removing exposed portions of the Si, Ge, III-V, or SixGe1-x substrate, forming second trenches; forming III-V, III-VxMy, or Si nanowires in the second trenches; removing the first mask and forming a second mask over the III-VxMy, or Si nanowires and intervening first trenches; removing the SiOx layer, forming third trenches; and removing the second mask.

公开(公告)号：US09588044B2

公开(公告)日：2017-03-07

申请号：US14800940

申请日：2015-07-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sabarinath Jayaseelan ,  Suraj Kumar Patil

IPC: G01N21/552 ,  G01N21/95

CPC classification number: G01N21/553 ,  G01N21/9501 ,  G01N21/95684

Abstract: A method and apparatus are provided for using SPR to detect buried voids in a semiconductor wafer inline post metal deposition. Embodiments include forming a first, a second, and a third metal structure in a first, a second, and a third adjacent die of a wafer; performing a SPR on the first, second, and third metal structures inline; detecting a first, a second, and a third SPR wavelength corresponding to the first, second, and third metal structures, respectively; comparing a difference between the first SPR wavelength and the second SPR wavelength and a difference between the third SPR wavelength and the first SPR wavelength against a threshold value; and determining a presence or an absence of a buried void in the first metal structure based on the comparison.

Abstract translation: 提供了一种使用SPR来检测半导体晶片在线后金属沉积中的掩埋空隙的方法和装置。 实施例包括在晶片的第一，第二和第三相邻晶片中形成第一，第二和第三金属结构; 在第一，第二和第三金属结构上进行SPR; 检测分别对应于第一，第二和第三金属结构的第一，第二和第三SPR波长; 将第一SPR波长和第二SPR波长之间的差与第三SPR波长与第一SPR波长之间的差相对于阈值进行比较; 以及基于所述比较来确定所述第一金属结构中存在或不存在所述掩埋空隙。

公开(公告)号：US10319642B2

公开(公告)日：2019-06-11

申请号：US15667305

申请日：2017-08-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj Kumar Patil ,  Ajey P. Jacob

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/115 ,  H01L29/788 ,  H01L27/092 ,  H01L29/49 ,  H01L21/302 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L21/8258

Abstract: A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include forming first trenches in a Si, Ge, III-V, or SixGe1-x substrate; forming a conformal SiN, SiOxCyNz layer over side and bottom surfaces of the first trenches; filling the first trenches with SiOx; forming a first mask over portions of the Si, Ge, III-V, or SixGe1-x substrate; removing exposed portions of the Si, Ge, III-V, or SixGe1-x substrate, forming second trenches; forming III-V, III-VxMy, or Si nanowires in the second trenches; removing the first mask and forming a second mask over the III-V, III-VxMy, or Si nanowires and intervening first trenches; removing the SiOx layer, forming third trenches; and removing the second mask.

公开(公告)号：US20170133319A1

公开(公告)日：2017-05-11

申请号：US14936582

申请日：2015-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj Kumar Patil ,  Min-Hwa Chi

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L23/535 ,  H01L23/62 ,  H01L27/11206 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146

Abstract: Methods, apparatus, and systems for fabricating and using a semiconductor device comprising a first conductive element; a second conductive element; and an e-fuse comprising a first region comprising a conductive oxide of a first metal; and a second region comprising a second metal, wherein an oxide of the second metal is resistive; wherein the e-fuse is electrically connected to both the first conductive element and the second conductive element.