公开(公告)号：US20180061976A1

公开(公告)日：2018-03-01

申请号：US15797634

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred J. Eller ,  Min-Hwa Chi ,  Jerome J. B. Ciavatti

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/783 ,  H01L27/1104 ,  H01L29/41775 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/66795

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate structure between a pair of gate spacers within a dielectric layer and substantially surrounding a fin, wherein the gate structure is disposed adjacent to a channel region within the fin; and a source/drain contact extending within the dielectric layer to a source/drain region within a fin, the source/drain contact being separated from the gate structure by at least one gate spacer in the pair of gate spacers, wherein the channel region and the source/drain region provide electrical connection between the gate structure and the source/drain contact.

公开(公告)号：US20170133319A1

公开(公告)日：2017-05-11

申请号：US14936582

申请日：2015-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj Kumar Patil ,  Min-Hwa Chi

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L23/535 ,  H01L23/62 ,  H01L27/11206 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146

Abstract: Methods, apparatus, and systems for fabricating and using a semiconductor device comprising a first conductive element; a second conductive element; and an e-fuse comprising a first region comprising a conductive oxide of a first metal; and a second region comprising a second metal, wherein an oxide of the second metal is resistive; wherein the e-fuse is electrically connected to both the first conductive element and the second conductive element.

公开(公告)号：US09006066B2

公开(公告)日：2015-04-14

申请号：US13871357

申请日：2013-04-26

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Min-Hwa Chi ,  Hoong Shing Wong

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7853 ,  H01L29/20 ,  H01L29/22 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure in fabrication includes a n-FinFET and p-FinFET. Stress inducing materials such as silicon and silicon germanium are epitaxially grown into naturally diamond-shaped structures atop the silicon fins of the n-FinFET and p-FinFET areas. The diamond structures act as the source, drain and channel between the source and drain. The diamond structures of the channel are selectively separated from the fin while retaining the fin connections of the diamond-shaped growth of the source and the drain. Further fabrication to complete the structure may then proceed.

Abstract translation: 制造中的半导体结构包括n-FinFET和p-FinFET。 诸如硅和硅锗的应力诱导材料在n-FinFET和p-FinFET区域的硅散热片的顶部外延生长成天然的菱形结构。 金刚石结构作为源极和漏极之间的源极，漏极和沟道。 通道的金刚石结构与翅片选择性分离，同时保持源极和漏极的菱形生长的翅片连接。 可以进一步完成结构的制造。

公开(公告)号：US20190043965A1

公开(公告)日：2019-02-07

申请号：US16147072

申请日：2018-09-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Min-Hwa Chi ,  Jinping Liu

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/088 ,  H01L29/78

Abstract: At least one method, apparatus and system disclosed herein fin field effect transistor (finFET) comprising a tall fin having a plurality of epitaxial regions. A first fin of a transistor is formed. The first fin comprising a first portion comprising silicon, a second portion comprising silicon germanium and a third portion comprising silicon. A gate structure above the third portion is formed. An etching process is performed for removing the silicon germanium of the second portion that is not below the gate structure. A first epitaxy region is formed above the first portion. A second epitaxy region is formed vertically aligned with the first epitaxy region and above the second region.

公开(公告)号：US10170377B1

公开(公告)日：2019-01-01

申请号：US15709704

申请日：2017-09-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-Hwa Chi

IPC: H01L21/8239 ,  H01L27/11 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: A method includes forming a device above an active region defined in a semiconducting substrate. The device includes a plurality of gate structures, a spacer formed adjacent each of the plurality of gate structures, and conductive source/drain contact structures positioned adjacent each of the plurality of gate structures and separated from the associated gate structure by the spacer. A first portion of the conductive source/drain contact structures of a subset of the plurality of gate structures is recessed at a first axial position along a selected gate structure of the plurality of gate structures to define a cavity. A selected source/drain contact structure is not recessed. A first dielectric layer is formed in the cavity. A conductive line contacting the selected source/drain contact structure in the first axial position is formed.

公开(公告)号：US10115807B2

公开(公告)日：2018-10-30

申请号：US15343821

申请日：2016-11-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Min-Hwa Chi ,  Jinping Liu

IPC: H01L21/30 ,  H01L29/66 ,  H01L29/08 ,  H01L21/306 ,  H01L21/02 ,  H01L29/78

Abstract: At least one method, apparatus and system disclosed herein fin field effect transistor (finFET) comprising a tall fin having a plurality of epitaxial regions. A first fin of a transistor is formed. The first fin comprising a first portion comprising silicon, a second portion comprising silicon germanium and a third portion comprising silicon. A gate structure above the third portion is formed. An etching process is performed for removing the silicon germanium of the second portion that is not below the gate structure. A first epitaxy region is formed above the first portion. A second epitaxy region is formed vertically aligned with the first epitaxy region and above the silicon germanium of the second portion that is below the gate structure.

公开(公告)号：US09761691B2

公开(公告)日：2017-09-12

申请号：US14560054

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Dong-Woon Shin ,  Min-Hwa Chi ,  Xusheng Wu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7848

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming sidewall spacer structures laterally adjacent to a dummy gate structure that overlies a semiconductor substrate. Additional sidewall spacer structures are formed laterally adjacent to the sidewall spacer structures and under lower portions of the sidewall spacer structures. The dummy gate structure is replaced with a replacement gate structure.

公开(公告)号：US20160111491A1

公开(公告)日：2016-04-21

申请号：US14983329

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. Jacob ,  Min-Hwa Chi

IPC: H01L29/06 ,  H01L29/161 ,  H01L29/78

CPC classification number: H01L29/0638 ,  H01L21/02164 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a fin defined on a substrate and a gate electrode structure formed above the fin. A channel region of the device is defined beneath the gate electrode structure and source/drain regions of the fin are defined adjacent the gate electrode structure. A dielectric layer is defined at least in the channel region. The dielectric layer includes oxygen and at least one of nitrogen, carbon or fluorine.

Abstract translation: 半导体器件包括限定在衬底上的翅片和形成在鳍片上方的栅电极结构。 器件的沟道区域被限定在栅极电极结构的下方，鳍的源极/漏极区域被限定为邻近栅电极结构。 至少在通道区域中限定介电层。 介电层包括氧和氮，碳或氟中的至少一种。

公开(公告)号：US09263587B1

公开(公告)日：2016-02-16

申请号：US14476830

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. Jacob ,  Min-Hwa Chi

IPC: H01L21/265 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L29/16 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092

CPC classification number: H01L29/0638 ,  H01L21/02164 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method includes forming an ion implant layer in a fin defined on a semiconductor substrate. The semiconductor substrate is annealed to convert the ion implant layer to a dielectric layer. A gate electrode structure is formed above the fin in a channel region after forming the ion implant layer. The fin is recessed in a source/drain region. A semiconductor material is epitaxially grown in the source/drain region.

Abstract translation: 一种方法包括在限定在半导体衬底上的翅片上形成离子注入层。 将半导体衬底退火以将离子注入层转换成电介质层。 在形成离子注入层之后的沟道区域中，在鳍的上方形成栅电极结构。 鳍片凹陷在源极/漏极区域中。 在源极/漏极区域中外延生长半导体材料。

公开(公告)号：US09831346B1

公开(公告)日：2017-11-28

申请号：US15220990

申请日：2016-07-27

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Hui Zang ,  Min-Hwa Chi

IPC: H01L29/78 ,  H01L23/522 ,  H01L23/532 ,  H01L29/66 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L29/785 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/7682 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/41791 ,  H01L29/6656 ,  H01L29/66795 ,  H01L2029/7858

Abstract: Fin field effect transistors (FinFETs) include air-gaps between adjacent metal contacts and/or between metal contacts and the transistor gate. The air-gaps are formed during non-conformal deposition of an isolation dielectric in conjunction with a metal-first process to form the conductive structures.