公开(公告)号：US20210098612A1

公开(公告)日：2021-04-01

申请号：US16784683

申请日：2020-02-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Pekarik ,  Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Herbert Ho ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first heterojunction bipolar transistor includes a first emitter, a first collector, and a first base layer having a portion positioned between the first emitter and the first collector. A second heterojunction bipolar transistor includes a second emitter, a second collector, and a second base layer having a portion positioned between the second emitter and the second collector. The first and second base layers each comprise silicon-germanium, the first base layer includes a first germanium profile, and the second base layer includes a second germanium profile that is identical to the first germanium profile.

公开(公告)号：US12230673B2

公开(公告)日：2025-02-18

申请号：US17708561

申请日：2022-03-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Michel Abou-Khalil ,  Steven M. Shank ,  Aaron Vallett ,  Sarah McTaggart ,  Rajendran Krishnasamy

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423

Abstract: Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. The structure includes a semiconductor substrate having a first surface, a recess in the first surface, and a second surface inside the first recess. The structure further includes a shallow trench isolation region extending from the first surface into the semiconductor substrate. The shallow trench isolation region is positioned to surround an active device region including the recess. A field-effect transistor includes a gate electrode positioned on a portion of the second surface.

公开(公告)号：US12119352B2

公开(公告)日：2024-10-15

申请号：US17647176

申请日：2022-01-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Uzma B. Rana ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L27/12 ,  H01L21/762

CPC classification number: H01L27/1207 ,  H01L21/76283

Abstract: An integrated circuit (IC) structure, a switch and related method, are disclosed. The IC structure includes an active device, e.g., a switch, over a bulk semiconductor substrate, and an isolation structure under the active device in the bulk semiconductor substrate. The isolation structure may include a trench isolation adjacent the active device in the bulk semiconductor substrate, a dielectric layer laterally adjacent the trench isolation and over the active device, and a porous semiconductor layer in the bulk semiconductor substrate under the dielectric layer laterally adjacent the trench isolation. The IC structure employs a lower cost, low resistivity bulk semiconductor substrate rather than a semiconductor-on-insulator (SOI) substrate, yet it has better performance characteristics for RF switches than an SOI substrate.

公开(公告)号：US12027582B2

公开(公告)日：2024-07-02

申请号：US17450003

申请日：2021-10-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Uzma B. Rana ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L29/06 ,  H01L23/66 ,  H01L27/088 ,  H01L27/12

CPC classification number: H01L29/0653 ,  H01L23/66 ,  H01L27/088 ,  H01L27/1203

Abstract: An integrated circuit (IC) structure includes an active device over a bulk semiconductor substrate, and an isolation structure around the active device in the bulk semiconductor substrate. The isolation structure includes: a polycrystalline isolation layer under the active device, a trench isolation adjacent the active device, and a porous semiconductor layer between the trench isolation and the bulk semiconductor substrate.

公开(公告)号：US11977258B1

公开(公告)日：2024-05-07

申请号：US18148029

申请日：2022-12-29

Applicant: GlobalFoundries U.S. Inc.

Inventor： Laura J. Silverstein ,  Steven M. Shank ,  Judson R. Holt ,  Yusheng Bian

IPC: G02B6/122 ,  G02B6/13 ,  G02B6/02 ,  G02B6/12

CPC classification number: G02B6/122 ,  G02B6/13 ,  G02B6/02042 ,  G02B6/02333 ,  G02B2006/121

Abstract: Disclosed are a structure with a substrate-embedded waveguide and a method of forming the structure. The waveguide includes cladding material lining a trench in a substrate, a core in the trench on the cladding material, and at least one cavity within the core. Each cavity extends from one end of the core toward the opposite end and contains a low refractive index material or is under vacuum so the waveguide is an arrow waveguide. An insulator layer is on the substrate and extends laterally over the waveguide and a semiconductor layer is on the insulator layer. Additionally, depending upon the embodiment, an additional waveguide can be aligned above the substrate-embedded waveguide either on the isolation region or on a waveguide extender that extends at least partially through the isolation region and the insulator layer to the waveguide.

公开(公告)号：US20240045156A1

公开(公告)日：2024-02-08

申请号：US17816790

申请日：2022-08-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Vibhor Jain ,  Steven M. Shank

IPC: G02B6/42

CPC classification number: G02B6/4212 ,  G02B6/4215 ,  G02B6/4295 ,  G02B6/4274

Abstract: A structure includes a dielectric waveguide, and at least one grating coupler adjacent the dielectric waveguide. Each grating coupler includes a set of parallel optofluidic grating channels oriented orthogonally to the dielectric waveguide. The structure may also include a radiation source operatively coupled to the dielectric waveguide, and an optical receiver such as a photosensor adjacent the grating coupler(s). The structure may be used as part of an optofluidic sensor system for, for example, biochemical applications.

公开(公告)号：US11848324B2

公开(公告)日：2023-12-19

申请号：US17483104

申请日：2021-09-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ephrem G. Gebreselasie ,  Steven M. Shank ,  Alain F. Loiseau ,  Robert J. Gauthier, Jr. ,  Michel J. Abou-Khalil ,  Ahmed Y. Ginawi

IPC: H01L27/06 ,  H01L23/525 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/823481 ,  H01L23/5256

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an eFuse and gate structure on a triple-well and methods of manufacture. The structure includes: a substrate comprising a bounded region; a gate structure formed within the bounded region; and an eFuse formed within the bounded region and electrically connected to the gate structure.

公开(公告)号：US11823948B2

公开(公告)日：2023-11-21

申请号：US17696348

申请日：2022-03-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uzma Rana ,  Anthony K. Stamper ,  Steven M. Shank ,  Brett T. Cucci

IPC: H01L27/00 ,  H01L21/76 ,  H01L27/06 ,  H01L21/762

CPC classification number: H01L21/76 ,  H01L21/762 ,  H01L27/0617

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.

公开(公告)号：US11817479B2

公开(公告)日：2023-11-14

申请号：US17449336

申请日：2021-09-29

Applicant: GlobalFoundries U.S. Inc.

Inventor： Uzma B. Rana ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/763 ,  H01L29/08 ,  H01L21/764 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/763 ,  H01L21/76224 ,  H01L29/0847

Abstract: A transistor includes a bulk semiconductor substrate, and first and second raised source/drain regions above the bulk semiconductor substrate. A gate is between the first and second raised source/drain regions. A first dielectric section is beneath the first raised source/drain region in the bulk semiconductor substrate, and a second dielectric section is beneath the second raised source/drain region in the bulk semiconductor substrate. A first air gap is defined in at least the first dielectric section under the first raised source/drain region, and a second air gap is defined in at least the second dielectric section under the second raised source/drain region. The air gaps reduce off capacitance of the bulk semiconductor structure to near semiconductor-on-insulator levels without the disadvantages of an air gap under the channel region.

公开(公告)号：US11803009B2

公开(公告)日：2023-10-31

申请号：US17680421

申请日：2022-02-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Yusheng Bian ,  Steven M. Shank ,  Judson Holt

IPC: G02B6/122 ,  G02B6/136 ,  H01L21/84

CPC classification number: G02B6/122 ,  G02B6/136 ,  H01L21/84

Abstract: Photonics structures including an optical component and methods of fabricating a photonics structure including an optical component. The photonics structure includes an optical component, a substrate having a cavity and a dielectric material in the cavity, and a dielectric layer positioned in a vertical direction between the optical component and the cavity. The optical component is positioned in a lateral direction to overlap with the cavity in the substrate.