公开(公告)号：US20080076217A1

公开(公告)日：2008-03-27

申请号：US11534135

申请日：2006-09-21

申请人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

发明人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.

摘要翻译： 非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。 相邻的串由浅沟槽隔离结构隔离。 具有倒T形浮置栅极的阵列可以以自对准的方式形成。

公开(公告)号：US08383479B2

公开(公告)日：2013-02-26

申请号：US12840081

申请日：2010-07-20

申请人： Vinod Robert Purayath ,  James K. Kai ,  Masaaki Higashitani ,  Takashi Orimoto ,  George Matamis ,  Henry Chien

发明人： Vinod Robert Purayath ,  James K. Kai ,  Masaaki Higashitani ,  Takashi Orimoto ,  George Matamis ,  Henry Chien

IPC分类号： H01L21/8247

CPC分类号： H01L21/76224 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L27/11573 ,  H01L29/788 ,  Y10S438/962 ,  Y10S977/774 ,  Y10S977/936

摘要： Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.

公开(公告)号：US20110020992A1

公开(公告)日：2011-01-27

申请号：US12840081

申请日：2010-07-20

申请人： Vinod Robert Purayath ,  James K. Kai ,  Masaaki Higashitani ,  Takashi Orimoto ,  George Matamis ,  Henry Chien

发明人： Vinod Robert Purayath ,  James K. Kai ,  Masaaki Higashitani ,  Takashi Orimoto ,  George Matamis ,  Henry Chien

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/3205

CPC分类号： H01L21/76224 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L27/11573 ,  H01L29/788 ,  Y10S438/962 ,  Y10S977/774 ,  Y10S977/936

摘要： Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.

摘要翻译： 基于纳米结构的电荷存储区域包括在非易失性存储器件中，并与制造选择栅极和外围电路集成。 在存储器阵列区域和外围电路区域上的衬底上施加一个或多个纳米结构涂层。 提供了用于从衬底的不需要的区域（例如选择栅极和外围晶体管的目标区域）去除纳米结构涂层的各种工艺。 在一个实例中，使用基于自组装的工艺来形成一个或多个纳米结构涂层，以选择性地在衬底的有源区上形成纳米结构。 自组装允许形成彼此电隔离的纳米结构的离散线，而不需要对纳米结构涂层进行图案化或蚀刻。

公开(公告)号：US08097498B2

公开(公告)日：2012-01-17

申请号：US12693322

申请日：2010-01-25

申请人： Vinod Robert Purayath ,  George Matamis ,  James Kai ,  Takashi Orimoto

发明人： Vinod Robert Purayath ,  George Matamis ,  James Kai ,  Takashi Orimoto

IPC分类号： H01L21/20

CPC分类号： H01L27/101 ,  H01L27/1021

摘要： A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.

公开(公告)号：US07915664B2

公开(公告)日：2011-03-29

申请号：US12105242

申请日：2008-04-17

申请人： Henry Chien ,  Takashi Orimoto ,  George Matamis ,  James Kai ,  Vinod R. Purayath

发明人： Henry Chien ,  Takashi Orimoto ,  George Matamis ,  James Kai ,  Vinod R. Purayath

IPC分类号： H01L29/788

CPC分类号： G11C8/10 ,  G11C8/04 ,  G11C11/5621 ,  G11C16/0483 ,  G11C19/00 ,  H01L21/28273 ,  H01L27/11521

摘要： A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the sidewall insulating layer and the raised source/drain regions instead of via the bottom insulating layer. The floating gate may have a uniform width or an inverted T shape. The raised source/drain regions may be epitaxially grown from the substrate, and may include a doped region above an undoped region so that the channel length is effectively extended from beneath the floating gate and up into the undoped regions, so that short channel effects are reduced. The ratio of the thicknesses of the sidewall insulating layer to the bottom insulating layer may be about 0.3 to 0.67.

摘要翻译： 一种非易失性存储系统，其中浮动栅极的侧壁绝缘层比底部绝缘层的厚度明显薄，并且其中设置有凸起的源极/漏极区域。 在编程或擦除期间，隧道主要通过侧壁绝缘层和凸起的源极/漏极区域而不是通过底部绝缘层发生。 浮动门可以具有均匀的宽度或倒T形。 凸起的源极/漏极区域可以从衬底外延生长，并且可以包括在未掺杂区域上方的掺杂区域，使得沟道长度从浮置栅极下方有效地延伸并且向上延伸到未掺杂区域，使得短沟道效应为 减少 侧壁绝缘层与底部绝缘层的厚度的比例可以为约0.3至0.67。

公开(公告)号：US07807529B2

公开(公告)日：2010-10-05

申请号：US11960513

申请日：2007-12-19

申请人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  James Kai

发明人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  James Kai

IPC分类号： H01L21/336

CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： Lithographically-defined spacing is used to define feature sizes during fabrication of semiconductor-based memory devices. Sacrificial features are formed over a substrate at a specified pitch having a line size and a space size defined by a photolithography pattern. Charge storage regions for storage elements are formed in the spaces between adjacent sacrificial features using the lithographically-defined spacing to fix a gate length or dimension of the charge storage regions in a column direction. Unequal line and space sizes at the specified pitch can be used to form feature sizes at less than the minimally resolvable feature size associated with the photolithography process. Larger line sizes can improve line-edge roughness while decreasing the dimension of the charge storage regions in the column direction. Additional charge storage regions for the storage elements can be formed over the charge storage regions so defined, such as by depositing and etching a second charge storage layer to form second charge storage regions having a dimension in the column direction that is less than the gate length of the first charge storage regions.

摘要翻译： 在制造基于半导体的存储器件期间，使用光刻定义的间距来定义特征尺寸。 牺牲特征以具有由光刻图案限定的线尺寸和空间尺寸的指定间距在衬底上形成。 用于存储元件的电荷存储区域使用光刻定义的间隔在相邻的牺牲特征之间的空间中形成，以将电荷存储区域的栅极长度或尺寸固定在列方向上。 可以使用指定间距处的不等的线和空间尺寸来形成小于与光刻工艺相关联的最小可解析特征尺寸的特征尺寸。 较大的线尺寸可以改善线边缘粗糙度，同时减小电荷存储区域在列方向上的尺寸。 存储元件的附加电荷存储区域可以形成在如此限定的电荷存储区域上，例如通过沉积和蚀刻第二电荷存储层以形成具有小于栅极长度的列方向尺寸的第二电荷存储区域 的第一电荷存储区域。

公开(公告)号：US07736973B2

公开(公告)日：2010-06-15

申请号：US12020428

申请日：2008-01-25

申请人： Takashi Orimoto ,  George Matamis ,  James Kai

发明人： Takashi Orimoto ,  George Matamis ,  James Kai

IPC分类号： H01L21/3205

CPC分类号： H01L27/11521 ,  H01L27/11519

摘要： Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming are provided. A charge storage layer is etched into strips extending across a substrate surface in a row direction with a tunnel dielectric layer therebetween. The resulting strips may be continuous in the row direction or may comprise individual charge storage regions if already divided along their length in the row direction. A second layer of dielectric material is formed along the sidewalls of the strips and over the tunnel dielectric layer in the spaces therebetween. The second layer is etched into regions overlaying the tunnel dielectric layer in the spaces between strips. An intermediate dielectric layer is formed along exposed portions of the sidewalls of the strips and over the second dielectric layer in the spaces therebetween. A layer of control gate material is deposited in the spaces between strips. The resulting control gates are separated from the strips by the intermediate dielectric layer and from the substrate surface by the tunnel dielectric layer, the second layer of dielectric material and the intermediate dielectric layer.

摘要翻译： 提供了具有双控制栅极存储单元的非易失性半导体存储器件和形成方法。 电荷存储层被蚀刻成沿着行方向延伸穿过衬底表面的条带，其间具有隧道介电层。 所得到的条带可以在行方向上是连续的，或者可以包括单独的电荷存储区域，如果沿着它们的行方向上的长度被划分。 第二层电介质材料沿着条的侧壁和隧道介电层之间的空间形成。 第二层被蚀刻到条带之间的空间中覆盖隧道介电层的区域中。 沿着条的侧壁的暴露部分和在它们之间的空间中的第二介电层上方形成中间介电层。 控制栅极材料层沉积在条带之间的空间中。 所得到的控制栅极通过中间介电层和通过隧道介电层，第二介电材料层和中间介质层从衬底表面与条分离。

公开(公告)号：US20100055889A1

公开(公告)日：2010-03-04

申请号：US12615154

申请日：2009-11-09

申请人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  James Kai

发明人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  James Kai

IPC分类号： H01L21/28

CPC分类号： H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

摘要： Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length or dimension in a column direction than a second charge storage region. While not required, the different regions can be formed of the same or similar materials, such as polysilicon. Etching a second charge storage layer selectively with respect to a first charge storage layer can be performed using an interleaving etch-stop layer. The first charge storage layer is protected from overetching or damage during etching of the second charge storage layer. Consistency in the dimensions of the individual memory cells can be increased.

摘要翻译： 包括具有复合电荷存储元件的存储器单元的基于半导体的非易失性存储器在形成存储元件的至少一部分期间使用蚀刻停止层制造。 适用于存储器应用的一个复合电荷存储元件包括具有比第二电荷存储区域在列方向上更大的栅极长度或尺寸的第一电荷存储区域。 虽然不需要，但是不同的区域可以由相同或相似的材料形成，例如多晶硅。 可以使用交错蚀刻停止层来执行相对于第一电荷存储层选择性地蚀刻第二电荷存储层。 第一电荷存储层在第二电荷存储层的蚀刻期间被保护以免过蚀或损坏。 可以增加各个存储单元尺寸的一致性。

公开(公告)号：US07939407B2

公开(公告)日：2011-05-10

申请号：US12615154

申请日：2009-11-09

申请人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  James Kai

发明人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  James Kai

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

摘要： Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length or dimension in a column direction than a second charge storage region. While not required, the different regions can be formed of the same or similar materials, such as polysilicon. Etching a second charge storage layer selectively with respect to a first charge storage layer can be performed using an interleaving etch-stop layer. The first charge storage layer is protected from overetching or damage during etching of the second charge storage layer. Consistency in the dimensions of the individual memory cells can be increased.

摘要翻译： 包括具有复合电荷存储元件的存储器单元的基于半导体的非易失性存储器在形成存储元件的至少一部分期间使用蚀刻停止层制造。 适用于存储器应用的一个复合电荷存储元件包括具有比第二电荷存储区域在列方向上更大的栅极长度或尺寸的第一电荷存储区域。 虽然不需要，但是不同的区域可以由相同或相似的材料形成，例如多晶硅。 可以使用交错蚀刻停止层来执行相对于第一电荷存储层选择性地蚀刻第二电荷存储层。 第一电荷存储层在第二电荷存储层的蚀刻期间被保护以免过蚀或损坏。 可以增加各个存储单元尺寸的一致性。

公开(公告)号：US20100178742A1

公开(公告)日：2010-07-15

申请号：US12729874

申请日：2010-03-23

申请人： Takashi Orimoto ,  George Matamis ,  Henry Chien ,  James Kai

发明人： Takashi Orimoto ,  George Matamis ,  Henry Chien ,  James Kai

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also.

摘要翻译： 一串串联的非易失性存储单元包括位于浮置栅极和下面的衬底表面之间的固定电荷。 这样的固定电荷会影响衬底的下层部分中电荷载流子的分布，从而影响器件的阈值电压。 固定电荷层也可以在源极/漏极区域上延伸。