摘要:
Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.
摘要:
Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.
摘要:
A method for fabricating a non-volatile storage element. The method comprises forming a layer of polysilicon floating gate material over a substrate and forming a layer of nitride at the surface of the polysilicon floating gate material. Floating gates are formed from the polysilicon floating gate material. Individual dielectric caps are formed from the nitride such that each individual nitride dielectric cap is self-aligned with one of the plurality of floating gates. An inter-gate dielectric layer is formed over the surface of the dielectric caps and the sides of the floating gates. Control gates are then formed with the inter-gate dielectric layer separating the control gates from the floating gates. The layer of nitride may be formed using SPA (slot plane antenna) nitridation. The layer of nitride may be formed prior to or after etching of the polysilicon floating gate material to form floating gates.
摘要:
A method for fabricating a non-volatile storage element. The method comprises forming a layer of polysilicon floating gate material over a substrate and forming a layer of nitride at the surface of the polysilicon floating gate material. Floating gates are formed from the polysilicon floating gate material. Individual dielectric caps are formed from the nitride such that each individual nitride dielectric cap is self-aligned with one of the plurality of floating gates. An inter-gate dielectric layer is formed over the surface of the dielectric caps and the sides of the floating gates. Control gates are then formed with the inter-gate dielectric layer separating the control gates from the floating gates. The layer of nitride may be formed using SPA (slot plane antenna) nitridation. The layer of nitride may be formed prior to or after etching of the polysilicon floating gate material to form floating gates.
摘要:
High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.
摘要:
High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.
摘要:
Methods of fabricating integrated circuit devices are provided using composite spacer formation processes. A composite spacer structure is used to pattern and etch the layer stack when forming select features of the devices. A composite storage structure includes a first spacer formed from a first layer of spacer material and second and third spacers formed from a second layer of spacer material. The process is suitable for making devices with line and space sizes at less then the minimum resolvable feature size of the photolithographic processes being used. Moreover, equal line and space sizes at less than the minimum feature size. In one embodiment, an array of dual control gate non-volatile flash memory storage elements is formed using composite spacer structures. When forming the active areas of the substrate, with overlying strips of a layer stack and isolation regions therebetween, a composite spacer structure facilitates equal lengths of the strips and isolation regions therebetween.
摘要:
Methods of fabricating integrated circuit devices are provided using composite spacer formation processes. A composite spacer structure is used to pattern and etch the layer stack when forming select features of the devices. A composite storage structure includes a first spacer formed from a first layer of spacer material and second and third spacers formed from a second layer of spacer material. The process is suitable for making devices with line and space sizes at less then the minimum resolvable feature size of the photolithographic processes being used. Moreover, equal line and space sizes at less than the minimum feature size are possible. In one embodiment, an array of dual control gate non-volatile flash memory storage elements is formed using composite spacer structures. When forming the active areas of the substrate, with overlying strips of a layer stack and isolation regions therebetween, a composite spacer structure facilitates equal lengths of the strips and isolation regions therebetween.
摘要:
A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.
摘要:
A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.