公开(公告)号：US20230063900A1

公开(公告)日：2023-03-02

申请号：US17524438

申请日：2021-11-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Man Gu ,  Jagar Singh ,  Haiting Wang ,  Jeffrey Johnson

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/735 ,  H01L29/737 ,  H01L29/06

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a collector having a raised portion, an emitter having a raised portion, and a base laterally arranged between the raised portion of the emitter and the raised portion of the collector. The base includes an intrinsic base layer and an extrinsic base layer stacked with the intrinsic base layer. The structure further includes a stress liner positioned to overlap with the raised portion of the collector, the raised portion of the emitter, and the extrinsic base layer.

公开(公告)号：US20230062747A1

公开(公告)日：2023-03-02

申请号：US17529002

申请日：2021-11-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Man Gu ,  Haiting Wang ,  Jagar Singh

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/735 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes a lateral bipolar junction transistor including an extrinsic base region and a bilayer dielectric spacer on sidewalls of the extrinsic base region, and a p-n junction positioned under the bilayer dielectric spacer between the extrinsic base region and at least an emitter region.

公开(公告)号：US11545575B2

公开(公告)日：2023-01-03

申请号：US16919225

申请日：2020-07-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Man Gu ,  Wenjun Li ,  Sudarshan Narayanan

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

Abstract: An integrated circuit (IC) structure includes a semiconductor fin having a first longitudinal extent and a second longitudinal extent. The semiconductor fin has an upper fin portion having a uniform lateral dimension in the first longitudinal extent and the second longitudinal extent, a first subfin portion under the upper fin portion in the first longitudinal extent having a first lateral dimension, and a second subfin portion under the upper fin portion in the second longitudinal extent having a second lateral dimension different than the first lateral dimension. The second subfin may be used in a drain extension region of a laterally-diffused metal-oxide semiconductor (LDMOS) device. The second subfin reduces subfin current and improves HCI reliability, regardless of the type of LDMOS device.

公开(公告)号：US11289474B2

公开(公告)日：2022-03-29

申请号：US16853137

申请日：2020-04-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Man Gu ,  Wang Zheng ,  Teng-Yin Lin ,  Halting Wang ,  Tung-Hsing Lee

IPC: H01L21/00 ,  H01L27/11 ,  H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L23/66 ,  H01P3/06

Abstract: Structures including a passive device and methods of forming such structures. Multiple fins are positioned on a substrate, and an interconnect structure is positioned over the substrate. The fins contain a polycrystalline semiconductor material, and the interconnect structure includes a passive device that is positioned over the fins. The passive device may be, for example, an inductor or a transmission line.

公开(公告)号：US11239366B2

公开(公告)日：2022-02-01

申请号：US16776938

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Wenjun Li ,  Man Gu ,  Baofu Zhu

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/08

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a semiconductor body, a first source/drain region includes an epitaxial semiconductor layer on a first portion of the semiconductor body, and a second source/drain region is positioned in a second portion of the semiconductor body. The gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the gate structure, and the second source/drain region is positioned adjacent to the second sidewall of the gate structure. The first source/drain region has a first width, and the second source/drain region has a second width that is greater than the first width.

公开(公告)号：US20210327872A1

公开(公告)日：2021-10-21

申请号：US16853137

申请日：2020-04-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Man Gu ,  Wang Zheng ,  Teng-Yin Lin ,  Haiting Wang ,  Tung-Hsing Lee

IPC: H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L23/66 ,  H01P3/06

Abstract: Structures including a passive device and methods of forming such structures. Multiple fins are positioned on a substrate, and an interconnect structure is positioned over the substrate. The fins contain a polycrystalline semiconductor material, and the interconnect structure includes a passive device that is positioned over the fins. The passive device may be, for example, an inductor or a transmission line.

公开(公告)号：US20210265342A1

公开(公告)日：2021-08-26

申请号：US16796326

申请日：2020-02-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Wenjun Li ,  Man Gu

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66

Abstract: Integrated circuit (IC) structures including buried insulator layer and methods for forming are provided. In a non-limiting example, a IC structure includes: a substrate; a first fin over the substrate; a source region and a drain region in the first fin; a first gate structure and a second gate structure over the first fin, the first and the second gate structures positioned between the source region and the drain region; and a buried insulator layer including a portion disposed under the first fin.

公开(公告)号：US20210242339A1

公开(公告)日：2021-08-05

申请号：US16776938

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S, Inc.

Inventor： Wenjun Li ,  Man Gu ,  Baofu Zhu

IPC: H01L29/78 ,  H01L29/08 ,  H01L21/8238

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a semiconductor body, a first source/drain region includes an epitaxial semiconductor layer on a first portion of the semiconductor body, and a second source/drain region is positioned in a second portion of the semiconductor body. The gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the gate structure, and the second source/drain region is positioned adjacent to the second sidewall of the gate structure. The first source/drain region has a first width, and the second source/drain region has a second width that is greater than the first width.