公开(公告)号：US20220005954A1

公开(公告)日：2022-01-06

申请号：US16919225

申请日：2020-07-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Man Gu ,  Wenjun Li ,  Sudarshan Narayanan

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: An integrated circuit (IC) structure includes a semiconductor fin having a first longitudinal extent and a second longitudinal extent. The semiconductor fin has an upper fin portion having a uniform lateral dimension in the first longitudinal extent and the second longitudinal extent, a first subfin portion under the upper fin portion in the first longitudinal extent having a first lateral dimension, and a second subfin portion under the upper fin portion in the second longitudinal extent having a second lateral dimension different than the first lateral dimension. The second subfin may be used in a drain extension region of a laterally-diffused metal-oxide semiconductor (LDMOS) device. The second subfin reduces subfin current and improves HCI reliability, regardless of the type of LDMOS device.

公开(公告)号：US20210249307A1

公开(公告)日：2021-08-12

申请号：US16783741

申请日：2020-02-06

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Man Gu ,  Wenjun Li

IPC: H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/08

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. First and second gate structures extend over a semiconductor body. The first gate structure includes a first sidewall and a second sidewall opposite the first sidewall, and the second gate structure includes a sidewall adjacent to the first sidewall of the first gate structure. A first source/drain region includes a first epitaxial semiconductor layer positioned between the first sidewall of the first gate structure and the sidewall of the second gate structure. A second source/drain region includes a second epitaxial semiconductor layer positioned adjacent to the second sidewall of the first gate structure. The first sidewall of the first gate structure and the sidewall of the second gate structure are separated by a distance that is greater than a width of the first epitaxial semiconductor layer.

公开(公告)号：US12132080B2

公开(公告)日：2024-10-29

申请号：US17452651

申请日：2021-10-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Man Gu ,  Wenjun Li

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/0696 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/785

Abstract: A FinFET includes a semiconductor fin, and a source region and a drain region in the same semiconductor fin. The drain region has a first fin height above a trench isolation; and the source region has a second fin height above the trench isolation. The first fin height is less than the second fin height. The FinFET may be used, for example, in a scaled laterally diffused metal-oxide semiconductor (LDMOS) application, and exhibits reduced parasitic capacitance for improved radio frequency (RF) performance. A drain extension region may have the first fin height, and a channel region may have the second fin height. A method of making the FinFET is also disclosed.

公开(公告)号：US11545575B2

公开(公告)日：2023-01-03

申请号：US16919225

申请日：2020-07-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Man Gu ,  Wenjun Li ,  Sudarshan Narayanan

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

Abstract: An integrated circuit (IC) structure includes a semiconductor fin having a first longitudinal extent and a second longitudinal extent. The semiconductor fin has an upper fin portion having a uniform lateral dimension in the first longitudinal extent and the second longitudinal extent, a first subfin portion under the upper fin portion in the first longitudinal extent having a first lateral dimension, and a second subfin portion under the upper fin portion in the second longitudinal extent having a second lateral dimension different than the first lateral dimension. The second subfin may be used in a drain extension region of a laterally-diffused metal-oxide semiconductor (LDMOS) device. The second subfin reduces subfin current and improves HCI reliability, regardless of the type of LDMOS device.

公开(公告)号：US11239366B2

公开(公告)日：2022-02-01

申请号：US16776938

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Wenjun Li ,  Man Gu ,  Baofu Zhu

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/08

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a semiconductor body, a first source/drain region includes an epitaxial semiconductor layer on a first portion of the semiconductor body, and a second source/drain region is positioned in a second portion of the semiconductor body. The gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the gate structure, and the second source/drain region is positioned adjacent to the second sidewall of the gate structure. The first source/drain region has a first width, and the second source/drain region has a second width that is greater than the first width.

公开(公告)号：US11158624B1

公开(公告)日：2021-10-26

申请号：US16857298

申请日：2020-04-24

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Wenjun Li ,  Chen Perkins Yan ,  Tamilmani Ethirajan ,  Cole E. Zemke

IPC: H01L27/08 ,  H01L27/02 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L21/8234 ,  H03F3/195 ,  H01L27/12

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to unitary Cascode cells with resistance and capacitance optimization, and methods of manufacture. The structure includes a common source FET (CS-FET) in a first portion of a single common semiconductor region, the CS-FET comprising a source region and a drain region, a common gate FET (CG-FET) in a second portion of the single common semiconductor region, the CG-FET comprising a source region and a drain region, and a doped connecting region of the single common semiconductor region, connecting the drain of the CS-FET and the source of the CG-FET.

公开(公告)号：US20210265342A1

公开(公告)日：2021-08-26

申请号：US16796326

申请日：2020-02-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Wenjun Li ,  Man Gu

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66

Abstract: Integrated circuit (IC) structures including buried insulator layer and methods for forming are provided. In a non-limiting example, a IC structure includes: a substrate; a first fin over the substrate; a source region and a drain region in the first fin; a first gate structure and a second gate structure over the first fin, the first and the second gate structures positioned between the source region and the drain region; and a buried insulator layer including a portion disposed under the first fin.

公开(公告)号：US20210242339A1

公开(公告)日：2021-08-05

申请号：US16776938

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S, Inc.

Inventor： Wenjun Li ,  Man Gu ,  Baofu Zhu

IPC: H01L29/78 ,  H01L29/08 ,  H01L21/8238

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a semiconductor body, a first source/drain region includes an epitaxial semiconductor layer on a first portion of the semiconductor body, and a second source/drain region is positioned in a second portion of the semiconductor body. The gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the gate structure, and the second source/drain region is positioned adjacent to the second sidewall of the gate structure. The first source/drain region has a first width, and the second source/drain region has a second width that is greater than the first width.

公开(公告)号：US11410998B2

公开(公告)日：2022-08-09

申请号：US16796326

申请日：2020-02-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Wenjun Li ,  Man Gu

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

Abstract: Integrated circuit (IC) structures including buried insulator layer and methods for forming are provided. In a non-limiting example, a IC structure includes: a substrate; a first fin over the substrate; a source region and a drain region in the first fin; a first gate structure and a second gate structure over the first fin, the first and the second gate structures positioned between the source region and the drain region; and a buried insulator layer including a portion disposed under the first fin.

公开(公告)号：US20220028854A1

公开(公告)日：2022-01-27

申请号：US16937821

申请日：2020-07-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Wenjun Li ,  Man Gu

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A semiconductor substrate includes a first region, a second region, and a first source/drain region in the first region. A semiconductor fin is located over the second region of the semiconductor substrate. The semiconductor fin extends laterally along a longitudinal axis to connect to the first region of the semiconductor substrate. The structure includes a second source/drain region including an epitaxial semiconductor layer coupled to the first semiconductor fin, and a gate structure that extends over the semiconductor fin. The gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the gate structure, and the second source/drain region is positioned adjacent to the second sidewall of the gate structure.