公开(公告)号：US07189662B2

公开(公告)日：2007-03-13

申请号：US10925793

申请日：2004-08-24

申请人： Kunal R. Parekh ,  Chandra V. Mouli ,  M. Ceredig Roberts ,  Fernando Gonzalez

发明人： Kunal R. Parekh ,  Chandra V. Mouli ,  M. Ceredig Roberts ,  Fernando Gonzalez

IPC分类号： H01L21/31

CPC分类号： H01L21/76801 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/785

摘要： The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor construction is passivated by subjecting the construction to an anneal at a temperature of greater than or equal to 350° C. while exposing the construction to a deuterium-enriched ambient.

摘要翻译： 本发明包括形成和/或钝化半导体结构的方法。 在具体方面，半导体衬底的各种氧化物可以通过将衬底的半导体材料暴露于富氘蒸汽来形成。 在其他方面，半导体结构通过在大于或等于350℃的温度下对该结构进行退火而钝化，同时将构造暴露于富氘化环境。

公开(公告)号：US07161857B2

公开(公告)日：2007-01-09

申请号：US11299868

申请日：2005-12-12

申请人： Kunal R. Parekh

发明人： Kunal R. Parekh

IPC分类号： G11C29/00

CPC分类号： G11C17/18 ,  G11C29/789

摘要： A method and apparatus is provided for performing a redundancy programming. The system of the present invention includes a device testing unit for performing a memory test. The system also includes a memory device operatively coupled to the device testing unit. The memory device includes an access transistor that includes a charge trapping area. A threshold voltage of the access transistor is modified upon trapping of charges in the charge trapping unit. The memory device also includes a memory element and a fuse associated with the memory element. The fuse is capable of entering an alternative state in response to modifying the threshold voltage of the access transistor. The state of the fuse may be used to program or de-program the memory element.

摘要翻译： 提供了一种用于执行冗余编程的方法和装置。 本发明的系统包括用于执行存储器测试的设备测试单元。 该系统还包括可操作地耦合到设备测试单元的存储器件。 存储器件包括存取晶体管，其包括电荷捕获区域。 在电荷俘获单元中捕获电荷时修改存取晶体管的阈值电压。 存储器件还包括存储器元件和与存储器元件相关联的保险丝。 响应于修改存取晶体管的阈值电压，熔丝能够进入替代状态。 熔丝的状态可用于对存储元件进行编程或解除编程。

公开(公告)号：US07119397B2

公开(公告)日：2006-10-10

申请号：US10768081

申请日：2004-02-02

申请人： Mark Fischer ,  Charles H. Dennison ,  Fawad Ahmed ,  Richard H. Lane ,  John K. Zahurak ,  Kunal R. Parekh

发明人： Mark Fischer ,  Charles H. Dennison ,  Fawad Ahmed ,  Richard H. Lane ,  John K. Zahurak ,  Kunal R. Parekh

IPC分类号： H01L29/06

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/28247 ,  H01L29/6656

摘要： A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.

摘要翻译： 公开了一种用于在诸如MOSFET访问装置的存储器阵列器件中形成扩散区的双层覆盖离子注入方法。 该方法提供了在其表面上形成栅极结构的半导体衬底。接下来，通过第一覆盖离子注入工艺在与沟道区相邻的区域中形成第一对扩散区。 第一次毯式离子注入工艺具有第一能级和剂量。 该器件经受氧化条件，其在栅极结构上形成氧化的侧壁。 在与第一离子注入工艺相同的位置处进行第二覆盖离子注入工艺，向扩散区域添加额外的掺杂剂。 第二次毯子离子注入过程具有第二能量水平和剂量。 所得到的扩散区域提供了比现有技术的装置更好的静态刷新性能的装置。 此外，第一和第二能量水平和剂量基本上低于现有技术单一植入过程中使用的能级和剂量。

公开(公告)号：US07006392B2

公开(公告)日：2006-02-28

申请号：US10764954

申请日：2004-01-26

申请人： Kunal R. Parekh

发明人： Kunal R. Parekh

IPC分类号： G11C7/00

CPC分类号： G11C17/18 ,  G11C29/789

摘要： A method and apparatus is provided for performing a redundancy programming. The system of the present invention includes a device testing unit for performing a memory test. The system also includes a memory device operatively coupled to the device testing unit. The memory device includes an access transistor that includes a charge trapping area. A threshold voltage of the access transistor is modified upon trapping of charges in the charge trapping unit. The memory device also includes a memory element and a fuse associated with the memory element. The fuse is capable of entering an alternative state in response to modifying the threshold voltage of the access transistor. The state of the fuse may be used to program or de-program the memory element.

摘要翻译： 提供了一种用于执行冗余编程的方法和装置。 本发明的系统包括用于执行存储器测试的设备测试单元。 该系统还包括可操作地耦合到设备测试单元的存储器件。 存储器件包括存取晶体管，其包括电荷捕获区域。 在电荷俘获单元中捕获电荷时修改存取晶体管的阈值电压。 存储器件还包括存储器元件和与存储器元件相关联的保险丝。 响应于修改存取晶体管的阈值电压，熔丝能够进入替代状态。 熔丝的状态可用于对存储元件进行编程或解除编程。

公开(公告)号：US06921692B2

公开(公告)日：2005-07-26

申请号：US10615287

申请日：2003-07-07

申请人： Kunal R. Parekh ,  Byron N. Burgess

发明人： Kunal R. Parekh ,  Byron N. Burgess

IPC分类号： G11C11/00 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L21/76897 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76895 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/907

摘要： The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging material is formed within the bit node contact opening between the pair of word lines. Sacrificial plugging material is removed from the bit node contact opening between the pair of word lines, and it is replaced with conductive material that is in electrical connection with the bit node. Thereafter, the conductive material is formed into a bit line.

公开(公告)号：US06617635B2

公开(公告)日：2003-09-09

申请号：US10039950

申请日：2001-12-31

申请人： Kunal R. Parekh ,  John K. Zahurak

发明人： Kunal R. Parekh ,  John K. Zahurak

IPC分类号： H01L27108

CPC分类号： H01L27/10894 ,  H01L27/10811 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/90

摘要： Integrated circuitry fabricated using methods for forming contact structures and container structures, as described herein, are provided. The integrated circuitry formed by the methods of the present invention, for example DRAM structures, provide capacitors in containers having sufficiently high storage capacitance for advanced integrated circuit devices. In addition the methods for forming such container capacitors facilitate the formation of contacts structures and provided for the formation of local interconnect structures and electrical contact to each of the structures formed.

摘要翻译： 提供了使用如本文所述形成接触结构和容器结构的方法制造的集成电路。 通过本发明的方法（例如DRAM结构）形成的集成电路在具有足够高的存储电容的容器中提供用于高级集成电路器件的电容器。 此外，用于形成这种容器电容器的方法有助于形成接触结构并且提供用于形成局部互连结构和与形成的每个结构的电接触。

公开(公告)号：US06605532B1

公开(公告)日：2003-08-12

申请号：US09858121

申请日：2001-05-15

申请人： Kunal R. Parekh ,  Mark Fischer ,  Charles H. Dennison

发明人： Kunal R. Parekh ,  Mark Fischer ,  Charles H. Dennison

IPC分类号： H01L214763

CPC分类号： H01L23/485 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

摘要： A network of electrically conductive plate contacts is provided within the structure of a DRAM chip to enable storage of non-zero voltage levels in each charge storage region. An improved cell or top plate contact provides low contact resistance and improved structural integrity making the contact less prone to removal during subsequent processing steps. A top plate conformally lines a container patterned down into a subregion. A metal contact structure comprises a waist section, a contact leg, and an anchor leg. The contact leg makes contact to the top plate within the container interior. The waist section joins the top of the contact leg to the top of the anchor leg and extends over the edge of the top plate. The anchor leg extends downward through the subregion adjacent to but spaced from the container to anchor the structure in place and provide structural integrity. Accordingly, the present invention provides an improved structure for contact to a conductive thin film, having low contact resistance and an improved structural integrity.

公开(公告)号：US06383887B1

公开(公告)日：2002-05-07

申请号：US09724752

申请日：2000-11-28

申请人： Kunal R. Parekh ,  John K. Zahurak ,  Phillip G. Wald

发明人： Kunal R. Parekh ,  John K. Zahurak ,  Phillip G. Wald

IPC分类号： H01L2120

CPC分类号： H01L27/10888 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L29/94 ,  Y10S438/964

摘要： The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively lo forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon. The invention also includes a capacitor comprising: a) a first capacitor plate; b) a second capacitor plate; c) a capacitor dielectric layer intermediate the first and second capacitor plates; and d) at least one of the first and second capacitor plates comprising a surface against the capacitor dielectric layer and wherein said surface comprises both doped rugged polysilicon and doped non-rugged polysilicon.

摘要翻译： 本发明包括许多与半导体电路技术有关的方法和结构，包括：形成DRAM存储单元结构的方法; 形成电容器结构的方法; DRAM存储单元结构; 电容器结构; 和单片集成电路。 本发明包括一种形成电容器的方法，包括以下步骤：a）在节点位置上形成硅材料块，所述质量包括暴露的掺杂硅和暴露的未掺杂硅; b）基本上选择性地从暴露的未掺杂硅而不是暴露的掺杂硅形成凹凸多晶硅; 以及c）在坚固的多晶硅和掺杂硅附近形成电容器电介质层和互补的电容器板。 本发明还包括一种电容器，包括：a）第一电容器板; b）第二电容器板; c）在第一和第二电容器板之间的电容器电介质层; 以及d）所述第一和第二电容器板中的至少一个包括抵抗所述电容器介电层的表面，并且其中所述表面包括掺杂的坚固的多晶硅和掺杂的非坚固的多晶硅。

公开(公告)号：US06372601B1

公开(公告)日：2002-04-16

申请号：US09146838

申请日：1998-09-03

申请人： David L. Dickerson ,  Richard H. Lane ,  Charles H. Dennison ,  Kunal R. Parekh ,  Mark Fischer ,  John K. Zahurak

发明人： David L. Dickerson ,  Richard H. Lane ,  Charles H. Dennison ,  Kunal R. Parekh ,  Mark Fischer ,  John K. Zahurak

IPC分类号： H01L21762

CPC分类号： H01L21/76232 ,  H01L21/0332 ,  H01L21/76235

摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.

公开(公告)号：US06331720B1

公开(公告)日：2001-12-18

申请号：US09511514

申请日：2000-02-22

申请人： Kunal R. Parekh ,  Zhiqiang Wu ,  Li Li

发明人： Kunal R. Parekh ,  Zhiqiang Wu ,  Li Li

IPC分类号： H01L2708

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/82

摘要： An electrically conductive structure, such as a capacitor is disclosed. A capacitor can be made by providing a space extending between a pair of gate stacks on a semiconductor substrate, the space exposing a charge conducting region on the semiconductor substrate. A BPSG layer is formed over the pair of gate stacks. A hard mask layer comprising alternating layers of doped polysilicon and undoped polysilicon is formed over the BPSG layer during a single deposition cycle of depositing polysilicon. Portions of the hard mask layer and the BPSG layer are selectively removed to form topographical structures extending above the gate stacks and having a trench therebetween. A spacer etch and a contact etch are performed to expose the charge conducting region. A doped polysilicon spacer is formed on the lateral side of each topographical structure. A second group of alternating layers of doped polysilicon and undoped polysilicon is formed over the topographical strictures and within the trenches. Portions of the hard mask layer and the second group of the alternating layers of doped polysilicon and undoped polysilicon are selectively removed. An etch selective to the doped polysilicon is performed to selectively remove the undoped polysilicon to create an electrically conductive structure with spaced apart doped polysilicon layers. A dielectric layer and an electrically conductive cell plate are formed over the alternating layers of the doped polysilicon and the undoped polysilicon. The semiconductor substrate is heated to diffuse dopant in the doped polysilicon into the undoped polysilicon. The resultant novel capacitor has fin-like structure extending therefrom which increase the surface area thereof.

摘要翻译： 公开了诸如电容器的导电结构。 可以通过在半导体衬底上的一对栅极堆叠之间提供延伸的空间来形成电容器，该空间暴露半导体衬底上的电荷导电区域。 在一对栅极叠层上形成BPSG层。 在沉积多晶硅的单个沉积循环期间，在BPSG层上形成包括掺杂多晶硅和未掺杂多晶硅交替层的硬掩模层。 选择性地去除硬掩模层和BPSG层的部分以形成在栅叠层之上延伸并且在它们之间具有沟槽的拓扑结构。 执行间隔物蚀刻和接触蚀刻以暴露电荷导电区域。 在每个形貌结构的侧面上形成掺杂的多晶硅间隔物。 掺杂多晶硅和未掺杂多晶硅的第二组交替层形成在形貌上的狭缝和沟槽内。 选择性地去除了硬掩模层和掺杂多晶硅和未掺杂多晶硅的交替层的第二组的部分。 执行对掺杂多晶硅的选择性蚀刻以选择性地去除未掺杂的多晶硅以产生具有间隔开的掺杂多晶硅层的导电结构。 在掺杂多晶硅和未掺杂多晶硅的交替层上形成介电层和导电单元板。 加热半导体衬底以将掺杂多晶硅中的掺杂剂扩散到未掺杂的多晶硅中。 所得到的新型电容器具有从其延伸的鳍状结构，其增加其表面积。