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21.发明授权Chaining multiple smaller store queue entries for more efficient store queue usage 有权链接多个较小的存储队列条目，以实现更高效的存储队列使用公开(公告)号：US08166246B2
公开(公告)日：2012-04-24
申请号：US12023600
申请日：2008-01-31
申请人： Guy Lynn Guthrie , Thomas Leo Jeremiah , William Lloyd McNeil , Hugh Shen , William John Starke
发明人： Guy Lynn Guthrie , Thomas Leo Jeremiah , William Lloyd McNeil , Hugh Shen , William John Starke
CPC分类号： G06F12/0893 , G06F12/0815
摘要： A computer implemented method, a processor chip, a data processing system, and computer program product in a data processing system process information in a store cache of a data processing system. The store cache receives a first entry that includes a first address indicating a first segment of a cache line. The store cache then receives a second entry including a second address indicating a second segment of the cache line. Responsive to the first segment not being equal to the second segment, the first entry is chained to the second entry.
摘要翻译： 数据处理系统中的计算机实现方法，处理器芯片，数据处理系统和计算机程序产品，处理数据处理系统的存储高速缓存中的信息。 存储高速缓存接收包括指示高速缓存行的第一段的第一地址的第一条目。 存储高速缓存然后接收包括指示高速缓存行的第二段的第二地址的第二条目。 响应于第一段不等于第二段，第一个条目链接到第二个条目。
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22.发明申请INFORMATION HANDLING SYSTEM WITH IMMEDIATE SCHEDULING OF LOAD OPERATIONS IN A DUAL-BANK CACHE WITH DUAL DISPATCH INTO WRITE/READ DATA FLOW 有权信息处理系统具有立即调度双币种缓存中的负载操作，双重分配到写/读数据流公开(公告)号：US20100268887A1
公开(公告)日：2010-10-21
申请号：US12424255
申请日：2009-04-15
申请人： Sanjeev Ghai , Guy Lynn Guthrie , Hugh Shen , William John Starke
发明人： Sanjeev Ghai , Guy Lynn Guthrie , Hugh Shen , William John Starke
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0811
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides dual dispatch points into the data flow to the dual cache banks of the L2 cache memory.
摘要翻译： 信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。 处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。 处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。 仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 L2高速缓冲存储器包括双数据库，使得一个存储体可以执行加载操作，而另一个存储体执行存储操作。 缓存系统向数据流提供双调度点到二级高速缓冲存储器的双缓存组。
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23.发明授权Data processing system and method for efficient coherency communication utilizing coherency domains 失效数据处理系统和方法，利用一致性域进行有效的一致性通信公开(公告)号：US08214600B2
公开(公告)日：2012-07-03
申请号：US11055402
申请日：2005-02-10
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/0831
摘要： In a cache coherent data processing system including at least first and second coherency domains, a master performs a first broadcast of an operation within the cache coherent data processing system that is limited in scope of transmission to the first coherency domain. The master receives a response of the first coherency domain to the first broadcast of the operation. If the response indicates the operation cannot be serviced in the first coherency domain alone, the master increases the scope of transmission by performing a second broadcast of the operation in both the first and second coherency domains. If the response indicates the operation can be serviced in the first coherency domain, the master refrains from performing the second broadcast.
摘要翻译： 在包括至少第一和第二相干域的高速缓存相干数据处理系统中，主器件在高速缓存相干数据处理系统内进行第一广播，其被限制在传输范围到第一相干域。 主机接收第一个一致性域的响应到该操作的第一次广播。 如果响应指示仅在第一个相干域中不能进行操作，则主设备通过在第一和第二相干域中执行操作的第二次广播来增加传输的范围。 如果响应指示可以在第一相干域中服务操作，则主机不执行第二广播。
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24.发明授权System bus structure for large L2 cache array topology with different latency domains 失效具有不同延迟域的大二级缓存阵列拓扑的系统总线结构公开(公告)号：US07793048B2
公开(公告)日：2010-09-07
申请号：US12207445
申请日：2008-09-09
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/0851 , Y02D10/13
摘要： A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory value from a second data bus over a second time span of successive clock cycles which overlaps with the first time span. In the illustrative embodiment a first input line is used for loading both a first byte array of the first cache line and a first byte array of the second cache line, a second input line is used for loading both a second byte array of the first cache line and a second byte array of the second cache line, and the transmission of the separate portions of the first and second memory values is interleaved between the first and second data busses.
摘要翻译： 一种高速缓冲存储器，其通过在连续时钟周期的第一时间间隔内从第一数据总线接收第一请求存储器值的分开的部分来将两个存储器值加载到两个高速缓存行中，并且从第二数据接收第二请求存储器值的分离部分 总线与第一时间跨度重叠的连续时钟周期的第二时间跨度。 在说明性实施例中，第一输入线用于加载第一高速缓存行的第一字节数组和第二高速缓存行的第一字节数组，第二输入行用于加载第一高速缓存的第二字节数组 线和第二高速缓存线的第二字节阵列，并且第一和第二存储器值的分离部分的传输在第一和第二数据总线之间交错。
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公开(公告)号：US07783842B2
公开(公告)日：2010-08-24
申请号：US10339764
申请日：2003-01-09
IPC分类号： G06F12/00
CPC分类号： G06F12/0835
摘要： A processing unit includes a processor core, an input/output (I/O) communication adapter coupled to the processor core, and a cache system coupled to the processor core and to the I/O communication adapter. The cache system including a cache array, a cache directory and a cache controller. The cache controller snoops I/O communication by the I/O communication adapter and, in response to snooping the I/O communication adapter performing an I/O data write of outgoing data in an exclusive state, invalidates corresponding data stored within the cache array.
摘要翻译： 处理单元包括处理器核心，耦合到处理器核心的输入/输出（I / O）通信适配器以及耦合到处理器核心和I / O通信适配器的高速缓存系统。 缓存系统包括缓存阵列，缓存目录和高速缓存控制器。 缓存控制器通过I / O通信适配器监听I / O通信，并且响应于窥探I / O通信适配器以独占状态执行输出数据的I / O数据写入，使存储在高速缓存阵列中的对应数据无效 。
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26.发明申请Enhanced Processor Virtualization Mechanism Via Saving and Restoring Soft Processor/System States 失效通过保存和恢复软处理器/系统状态来增强处理器虚拟化机制公开(公告)号：US20090157945A1
公开(公告)日：2009-06-18
申请号：US12352462
申请日：2009-01-12
CPC分类号： G06F9/30123 , G06F9/30116 , G06F9/3013 , G06F9/462
摘要： A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.
摘要翻译： 公开了一种方法和系统，用于在接收到处理器的处理中断时，保存对于在处理器中执行处理不重要的软状态信息。 软状态经由存储器接口传送到与处理器相关联的存储器。 优选地，软状态在处理器内经由处理器内的扫描链路径在处理器内传送到存储器接口，这允许功能数据路径通过软状态的存储而保持不受阻碍。 此后，当再次执行处理时，可以从存储器恢复存储的软状态。
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27.发明授权Cache directory array recovery mechanism to support special ECC stuck bit matrix 失效缓存目录数组恢复机制，支持特殊ECC卡位矩阵公开(公告)号：US07272773B2
公开(公告)日：2007-09-18
申请号：US10418546
申请日：2003-04-17
CPC分类号： G06F12/0802 , G06F11/1064
摘要： A method of correcting an error in an ECC protected mechanism of a computer system, such as a cache or system bus, by applying data with a number of bits N to an error correction code (ECC) matrix to yield an error detection syndrome, wherein the ECC matrix has a plurality of rows and columns with a given column corresponding to a respective one of the data bits, and selected bits are set in the ECC matrix along each column and each row such that encoding for the ECC matrix allows N-bit error correction and (N−1)-bit error detection. When an error is detected and after it is corrected, the corrected data is inverted and then rewritten to the cache array. The corresponding inversion bit for this entry is accordingly set to indicate that the data as currently stored is inverted.
摘要翻译： 一种通过将具有多个位N的数据应用于纠错码（ECC）矩阵来校正诸如高速缓存或系统总线的计算机系统的ECC保护机制中的错误的方法，以产生错误检测综合征，其中 ECC矩阵具有多个行和列，给定列对应于相应的一个数据位，并且所选择的位在每个列和每行的ECC矩阵中被设置，使得对于ECC矩阵的编码允许N位 纠错和（N-1）位错误检测。 当检测到错误并且在其被校正之后，校正的数据被反转，然后被重写到高速缓存阵列。 因此，该条目的相应的反转位被设置为指示当前存储的数据被反转。
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公开(公告)号：US07117319B2
公开(公告)日：2006-10-03
申请号：US10313321
申请日：2002-12-05
IPC分类号： G06F12/00
CPC分类号： G06F9/462 , G01R31/318536 , G06F9/30101 , G06F9/30116 , G06F9/3012 , G06F9/3013
摘要： A method and system are disclosed for managing a hard architected state of a processor that is critical for executing a process in the processor. A shadow copy of the hard architected state is stored from the processor to memory when an interrupt is received by the processor. The shadow copy of the hard architected permits rapid saving of the hard architected state for the interrupted process, so that the architected state of a next process can be immediately stored in the processor.
摘要翻译： 公开了一种用于管理对于在处理器中执行处理至关重要的处理器的硬结构状态的方法和系统。 当处理器接收到中断时，硬设计状态的卷影副本从处理器存储到存储器。 硬架构的卷影副本允许快速保存中断过程的硬结构状态，从而可以将下一个进程的架构状态立即存储在处理器中。
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29.发明授权Acceleration of input/output (I/O) communication through improved address translation 失效通过改进地址转换来加速输入/输出（I / O）通信公开(公告)号：US06976148B2
公开(公告)日：2005-12-13
申请号：US10339766
申请日：2003-01-09
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/1081
摘要： An I/O communication adapter receives from a processor core an I/O command referencing an effective address within an effective address space of the processor core that identifies a storage location. In response to receipt of the I/O command, the I/O communication adapter translates the effective address into a real address by reference to a translation data structure. The I/O communication adapter then accesses the storage location utilizing the real address to perform an I/O data transfer specified by the I/O command.
摘要翻译： I / O通信适配器从处理器核心接收参考在处理器核心的有效地址空间内识别存储位置的有效地址的I / O命令。 响应于I / O命令的接收，I / O通信适配器通过参考翻译数据结构将有效地址转换成实地址。 然后，I / O通信适配器使用实际地址访问存储位置，以执行由I / O命令指定的I / O数据传输。
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30.发明授权High performance multiprocessor system with exclusive-deallocate cache state 失效具有独占解除缓存状态的高性能多处理器系统公开(公告)号：US06385702B1
公开(公告)日：2002-05-07
申请号：US09437198
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/0811
摘要： A cache coherency protocol uses a “Exclusive-Deallocate” (ED) coherency state to indicate that a particular value is currently held in an upper level cache in an exclusive, unmodified form (not shared with any other caches of the computer system, including caches associated with the same processing unit), so that the value can conveniently be modified without any lower level bus transactions since no lower level caches have allocated a line for the value. If the value is subsequently modified in the upper level cache, its coherency state is simply switched to “modified” without the need for any bus transactions. Conversely, if the value is evicted from the upper level cache without ever having been modified, it can be loaded into the lower level cache with a coherency state indicating that the lower level cache contains the unmodified value exclusive of all other caches in other processing units of the computer system. If the value is initially loaded into the upper level cache from a cache of another processing unit, or from a lower level cache of the same processing unit, then the upper level cache may be selectively programmed to mark the cache line with the ED state.
摘要翻译： 高速缓存一致性协议使用“独占解除分配”（ED）一致性状态来指示特定值当前以独占未修改的形式（不与计算机系统的任何其他高速缓存共享，包括高速缓存）保持在高级缓存中 与相同的处理单元关联），使得该值可以方便地被修改而没有任何较低级别的总线事务，因为没有较低级别的高速缓存已经为该值分配了一行。 如果该值随后在高级缓存中被修改，则其一致性状态被简单地切换到“修改”，而不需要任何总线事务。 相反，如果该值从上级缓存中被逐出而没有被修改，则可以将其加载到具有一致性状态的相关性状态中，该相关性状态指示低级缓存包含其他处理单元中所有其他高速缓存的排他性的未修改值 的计算机系统。 如果该值最初从另一处理单元的高速缓存或相同处理单元的较低级高速缓存加载到高级缓存中，则可以选择性地编程高级缓存以用ED状态标记高速缓存行。
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