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    DELAY LOCKED LOOP CIRCUIT OF SEMICONDUCTOR DEVICE
    22.
    发明申请
    DELAY LOCKED LOOP CIRCUIT OF SEMICONDUCTOR DEVICE 有权
    半导体器件的延迟锁定环路电路

    公开(公告)号：US20090116306A1

    公开(公告)日：2009-05-07

    申请号：US12262517

    申请日：2008-10-31

    申请人： Hee-Woong SONG ,  Kun-Woo Park ,  Yong-Ju Kim ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee

    发明人： Hee-Woong SONG ,  Kun-Woo Park ,  Yong-Ju Kim ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee

    IPC分类号： G11C7/00 ,  G11C8/18 ,  H03L7/06

    CPC分类号： G11C29/02 ,  G11C7/22 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  H03L7/0812 ,  H03L7/089 ,  H03L7/095

    摘要： A semiconductor memory device includes a delay locked loop circuit that can control input/output timing of data according to a system clock of a high frequency. The semiconductor memory device includes a phase comparator configured to detect a phase difference between an internal clock and a reference clock to output a state signal having a pulse width corresponding to the detected phase difference, a phase adjuster configured to generate a digital code for determining a delay time corresponding to the state signal for locking a phase of the internal clock, a digital-to-analog converter configured to convert the digital code to an analog voltage, and a multiphase delay signal generator configured to delay the internal clock according to a bias voltage corresponding to the analog voltage to feed back the delayed internal clock as the internal clock and generate multiphase delay signals.

    摘要翻译： 半导体存储器件包括可以根据高频系统时钟控制数据的输入/输出定时的延迟锁定环电路。 半导体存储装置包括：相位比较器，被配置为检测内部时钟和参考时钟之间的相位差，以输出具有与检测到的相位差相对应的脉冲宽度的状态信号;相位调整器，被配置为生成用于确定 对应于用于锁定内部时钟的相位的状态信号的延迟时间，配置成将数字代码转换为模拟电压的数模转换器，以及被配置为根据偏置来延迟内部时钟的多相延迟信号发生器 对应于模拟电压的电压反馈延迟的内部时钟作为内部时钟，并产生多相延迟信号。

    Integrated circuit
    23.
    发明授权
    Integrated circuit 有权
    集成电路

    公开(公告)号：US08610475B2

    公开(公告)日：2013-12-17

    申请号：US12981764

    申请日：2010-12-30

    申请人： Yong-Ju Kim ,  Seong-Jun Lee ,  Hae-Rang Choi ,  Jae-Min Jang

    发明人： Yong-Ju Kim ,  Seong-Jun Lee ,  Hae-Rang Choi ,  Jae-Min Jang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0816

    摘要： An integrated circuit includes a delay locked loop configured to delay a reference clock signal by a delay time for delay locking and generate a delay locked clock signal, a clock transmission circuit configured to transmit the delay locked clock signal in response to a clock transmission signal, a duty correction circuit configured to perform duty correction operation on an output clock signal of the clock transmission circuit, and a clock transmission signal generation circuit configured to generate the clock transmission signal in response to a command and burst length information.

    摘要翻译： 一种集成电路包括：延迟锁定环路，被配置为延迟参考时钟信号延迟锁定的延迟时间，并产生延迟锁定时钟信号;时钟传输电路，被配置为响应于时钟传输信号传输延迟锁定时钟信号; 配置为对时钟发送电路的输出时钟信号进行占空比校正操作的占空比校正电路，以及响应于命令和突发长度信息而生成时钟发送信号的时钟发送信号生成电路。

    Delay locked loop
    24.
    发明授权
    Delay locked loop 有权
    延迟锁定环路

    公开(公告)号：US08319535B2

    公开(公告)日：2012-11-27

    申请号：US13111568

    申请日：2011-05-19

    申请人： Jae-Min Jang ,  Yong-Ju Kim ,  Hae-Rang Choi

    发明人： Jae-Min Jang ,  Yong-Ju Kim ,  Hae-Rang Choi

    IPC分类号： H03L7/06

    CPC分类号： H03L7/087 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0816

    摘要： A DLL circuit includes a common delay line configured to generate a delay locked clock by selectively delaying a source clock by one or more unit delays in response to a first delay control code or a second delay control code, a clock cycle detector configured to compare a phase of the source clock with a phase of the delay locked clock in a cycle detection mode and generate the first delay control code corresponding to a delay amount of a cycle of the source clock based on a result of comparing the phases of the source and delay locked clocks, a feedback delay configured to delay the delay locked clock and output a feedback clock, and a delay amount controller configured to compare the phase of the source clock with a phase of the feedback clock in a delay locking mode and change the second delay control code based on a result of comparing the source and feedback clocks.

    摘要翻译： DLL电路包括公共延迟线，其配置为通过响应于第一延迟控制代码或第二延迟控制代码选择性地将源时钟延迟一个或多个单位延迟来产生延迟锁定时钟，时钟周期检测器被配置为 源时钟的相位以延迟锁定时钟的相位处于周期检测模式，并且基于比较源极和延迟的相位的结果生成与源时钟的周期的延迟量相对应的第一延迟控制代码 锁定时钟，被配置为延迟延迟锁定时钟并输出反馈时钟的反馈延迟，以及延迟量控制器，被配置为将延迟锁定模式中的源时钟的相位与反馈时钟的相位进行比较，并且改变第二延迟 基于比较源和反馈时钟的结果的控制代码。

    Voltage level comparison circuit of semiconductor memory apparatus, voltage adjustment circuit using voltage level comparison circuit, and semiconductor memory apparatus using the same
    26.
    发明授权
    Voltage level comparison circuit of semiconductor memory apparatus, voltage adjustment circuit using voltage level comparison circuit, and semiconductor memory apparatus using the same 失效
    半导体存储装置的电压电平比较电路，使用电压电平比较电路的电压调整电路和使用其的半导体存储装置

    公开(公告)号：US08023356B2

    公开(公告)日：2011-09-20

    申请号：US12336423

    申请日：2008-12-16

    申请人： Ic-Su Oh ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee ,  Jae-Min Jang ,  Chang-Kun Park

    发明人： Ic-Su Oh ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee ,  Jae-Min Jang ,  Chang-Kun Park

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147

    摘要： A voltage adjustment circuit of a semiconductor memory apparatus includes a control voltage generating unit configured to distribute an external voltage for selectively outputting a plurality of distribution voltages as a control voltage in response to a control signal, the plurality of the distribution voltages each have different voltage levels, a comparing unit configured to include a voltage supply unit configured to control an external voltage supplied to a first node and a second node if a level of an output voltage is higher than a level of a reference voltage in response to a level of the control voltage, and a detection signal generating unit configured to drop potential levels of the first and second nodes according to the levels of the output voltage and the reference voltage, and to output the potential level of the second node as a detection signal, and a voltage generating unit configured to drive the external voltage according to a potential level of the detection signal and to output the external voltage as the output voltage.

    摘要翻译： 半导体存储装置的电压调整电路包括：控制电压生成部，其被配置为响应于控制信号分配用于选择性地输出多个分配电压的外部电压作为控制电压，所述多个分配电压各自具有不同的电压 电平，比较单元，被配置为包括电压供应单元，其被配置为响应于所述电平的电平而控制提供给第一节点的外部电压和第二节点，如果输出电压的电平高于参考电压的电平 以及检测信号生成单元，被配置为根据输出电压和参考电压的电平来降低第一和第二节点的电位电平，并输出第二节点的电位电平作为检测信号，以及 电压产生单元，被配置为根据检测信号的电位来驱动外部电压 并输出外部电压作为输出电压。

    Delay locked loop circuit of semiconductor device
    27.
    发明授权
    Delay locked loop circuit of semiconductor device 有权
    半导体器件的延迟锁定环路

    公开(公告)号：US07990785B2

    公开(公告)日：2011-08-02

    申请号：US12262517

    申请日：2008-10-31

    申请人： Hee-Woong Song ,  Kun-Woo Park ,  Yong-Ju Kim ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee

    发明人： Hee-Woong Song ,  Kun-Woo Park ,  Yong-Ju Kim ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee

    IPC分类号： G11C7/00

    CPC分类号： G11C29/02 ,  G11C7/22 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  H03L7/0812 ,  H03L7/089 ,  H03L7/095

    摘要： A semiconductor memory device includes a delay locked loop circuit that can control input/output timing of data according to a system clock of a high frequency. The semiconductor memory device includes a phase comparator configured to detect a phase difference between an internal clock and a reference clock to output a state signal having a pulse width corresponding to the detected phase difference, a phase adjuster configured to generate a digital code for determining a delay time corresponding to the state signal for locking a phase of the internal clock, a digital-to-analog converter configured to convert the digital code to an analog voltage, and a multiphase delay signal generator configured to delay the internal clock according to a bias voltage corresponding to the analog voltage to feed back the delayed internal clock as the internal clock and generate multiphase delay signals.

    摘要翻译： 半导体存储器件包括可以根据高频系统时钟控制数据的输入/输出定时的延迟锁定环电路。 半导体存储装置包括：相位比较器，被配置为检测内部时钟和参考时钟之间的相位差，以输出具有与检测到的相位差相对应的脉冲宽度的状态信号;相位调整器，被配置为生成用于确定 对应于用于锁定内部时钟的相位的状态信号的延迟时间，配置成将数字代码转换为模拟电压的数模转换器，以及被配置为根据偏置来延迟内部时钟的多相延迟信号发生器 对应于模拟电压的电压反馈延迟的内部时钟作为内部时钟，并产生多相延迟信号。

    Receiver circuit for use in a semiconductor integrated circuit
    28.
    发明授权
    Receiver circuit for use in a semiconductor integrated circuit 失效
    用于半导体集成电路的接收器电路

    公开(公告)号：US07868663B2

    公开(公告)日：2011-01-11

    申请号：US12171214

    申请日：2008-07-10

    申请人： Ic-Su Oh ,  Kun-Woo Park ,  Yong-Ju Kim ,  Hee-Woong Song ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee

    发明人： Ic-Su Oh ,  Kun-Woo Park ,  Yong-Ju Kim ,  Hee-Woong Song ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee

    IPC分类号： G01R19/00 ,  G11C7/00 ,  H03F3/45

    CPC分类号： H04L7/0337

    摘要： A receiver circuit for sensing and transmitting input data in sync with a plurality of clock signals having mutually different phase sequentially enabled comprising a sense amplifier configured to receive, as offset voltages, first signals which can be obtained by amplifying the input data in sync with a first clock signal of the plurality of clock signals, being driven in sync with a second clock signal enabled subsequently to the first clock signal, and outputting second signals, and a discharging controller configured to control a discharging speed of the sense amplifier according to the offset voltages to control a driven speed of the sense amplifier.

    摘要翻译： 一种接收机电路，用于与具有相互不同相位的多个时钟信号同步地感测和发送输入数据，其顺序地使能，包括读出放大器，其被配置为接收作为偏移电压的第一信号，所述第一信号可以通过与 所述多个时钟信号的第一时钟信号与与所述第一时钟信号之后使能的第二时钟信号同步地驱动，并输出第二信号;以及放电控制器，被配置为根据所述偏移来控制所述读出放大器的放电速度 电压来控制读出放大器的驱动速度。

    SEMICONDUCTOR MEMORY DEVICE
    29.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20100315139A1

    公开(公告)日：2010-12-16

    申请号：US12494403

    申请日：2009-06-30

    申请人： Hyung-Soo Kim ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Ic-Su Oh ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee ,  Jae-Min Jang ,  Chang-Kun Park

    发明人： Hyung-Soo Kim ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Ic-Su Oh ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee ,  Jae-Min Jang ,  Chang-Kun Park

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0816 ,  G11C7/1066 ,  G11C7/222 ,  H03L7/0805

    摘要： A semiconductor memory device is able to generate an output enable signal in response to a read command and CAS latency information. The semiconductor memory device includes a delay locked loop configured to detect a phase difference of an external clock signal and a feedback clock signal, generate a delay control signal corresponding to the detected phase difference, and generate a DLL clock signal by delaying the external clock signal for a time corresponding to the delay control signal, a delay configured to output an active signal as an output enable reset signal in response to the delay control signal and an output enable signal generator configured to be reset in response to the output enable reset signal and generate an output enable signal in response to a read signal and a CAS latency signal by counting the external clock signal and the DLL clock signal.

    摘要翻译： 半导体存储器件能够响应于读取命令和CAS延迟信息而产生输出使能信号。 半导体存储器件包括：延迟锁定环，被配置为检测外部时钟信号和反馈时钟信号的相位差，产生对应于检测到的相位差的延迟控制信号，并通过延迟外部时钟信号产生DLL时钟信号 延迟一段时间对应于延迟控制信号，延迟配置为响应于延迟控制信号而输出有效信号作为输出使能复位信号;以及输出使能信号发生器，其被配置为响应于输出使能复位信号复位;以及 通过对外部时钟信号和DLL时钟信号进行计数，响应于读取信号和CAS等待时间信号产生输出使能信号。

    Data output circuit for semiconductor memory apparatus
    30.
    发明授权
    Data output circuit for semiconductor memory apparatus 有权
    半导体存储装置的数据输出电路

    公开(公告)号：US07808841B2

    公开(公告)日：2010-10-05

    申请号：US12169568

    申请日：2008-07-08

    申请人： Hae-Rang Choi ,  Kun-Woo Park ,  Yong-Ju Kim ,  Hee-Woong Song ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Ji-Wang Lee

    发明人： Hae-Rang Choi ,  Kun-Woo Park ,  Yong-Ju Kim ,  Hee-Woong Song ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Ji-Wang Lee

    IPC分类号： G11C7/10 ,  G11C7/06 ,  G11C7/00

    CPC分类号： G11C7/1051 ,  G11C7/1057 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/50

    摘要： A data output circuit for a semiconductor memory apparatus includes a driver control signal generating unit that has a plurality of control signal generating units, each of which generates a driver unit control signal in response to a test signal during a test, and generates the driver unit control signal according to whether or not a fuse is cut after the test is completed, a first driver that has a plurality of driver units, each of which is activated in response to the driver unit control signal to drive a first data signal as an input signal and to output the driven first data signal to an output node, a signal combining unit that generates a first driver control signal in response to the driver unit control signal and an enable signal, and a second driver that has a plurality of driver units, each of which is activated in response to the first driver control signal to drive a second data signal as an input signal and to output the driven second data signal to the output node, and the number of driver units being two or more times as much as the number of driver units in the first driver. A voltage level on the output node is the voltage level of an output signal.

    摘要翻译： 一种用于半导体存储装置的数据输出电路，包括具有多个控制信号生成单元的驱动器控制信号生成单元，每个控制信号生成单元响应于测试期间的测试信号生成驱动单元控制信号，并且生成驱动单元 根据在测试完成之后是否切断熔丝的控制信号，具有多个驱动单元的第一驱动器，每个驱动器单元响应于驱动单元控制信号被激活以驱动第一数据信号作为输入 信号并将驱动的第一数据信号输出到输出节点;响应于驱动单元控制信号和使能信号产生第一驱动器控制信号的信号组合单元，以及具有多个驱动器单元的第二驱动器， 其中的每一个响应于第一驱动器控制信号被激活，以驱动第二数据信号作为输入信号，并将驱动的第二数据信号输出到输出节点;以及 驱动器单元的数量是第一驱动器中的驱动器单元的数量的两倍或更多倍。 输出节点上的电压电平是输出信号的电压电平。