公开(公告)号：US5990857A

公开(公告)日：1999-11-23

申请号：US841585

申请日：1997-04-30

申请人： Yasushi Kubota ,  Kenichi Katoh ,  Jun Koyama ,  Hidehiko Chimura ,  Yukio Tanaka

发明人： Yasushi Kubota ,  Kenichi Katoh ,  Jun Koyama ,  Hidehiko Chimura ,  Yukio Tanaka

IPC分类号： G09G3/20 ,  G09G3/36 ,  G11C19/00

CPC分类号： G09G3/3685 ,  G09G3/3648 ,  G09G3/3666 ,  G09G2310/0286 ,  G09G2330/021

摘要： The shift register of this invention for sequentially transferring a digital signal in synchronization with a clock signal includes: a plurality of circuit blocks connected in series, each including a prescribed number of sequential latch circuits, each latch circuit outputting a signal corresponding to an input signal based on the clock signal; and a plurality of clock signal control circuits provided for the respective circuit blocks for controlling the supply of the clock signal to the latch circuits in the corresponding circuit blocks, wherein the control of the supply of the clock signal by each clock signal control circuit to the latch circuits in the corresponding circuit block is conducted in response to output signals from prescribed latch circuits in the circuit blocks preceding and subsequent to the corresponding circuit block.

摘要翻译： 本发明的用于与时钟信号同步地顺序传送数字信号的移位寄存器包括：串联连接的多个电路块，每个电路块包括规定数量的顺序锁存电路，每个锁存电路输出对应于输入信号的信号 基于时钟信号; 以及多个时钟信号控制电路，用于各个电路块，用于控制向对应的电路块中的锁存电路提供时钟信号，其中控制由每个时钟信号控制电路将时钟信号提供给 响应于相应电路块之前和之后的电路块中来自规定的锁存电路的输出信号，进行相应电路块中的锁存电路。

公开(公告)号：US5926234A

公开(公告)日：1999-07-20

申请号：US877567

申请日：1997-06-17

申请人： Ichiro Shiraki ,  Yasushi Kubota ,  Hiroshi Yoneda

发明人： Ichiro Shiraki ,  Yasushi Kubota ,  Hiroshi Yoneda

IPC分类号： G02F1/136 ,  G02F1/133 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/36 ,  H01L29/78 ,  H01L29/786 ,  G02F1/1333 ,  G02F1/1345 ,  H01L23/62

CPC分类号： G02F1/13454 ,  G02F1/136204 ,  G02F2001/136254 ,  G09G3/3611 ,  H01L2924/0002

摘要： Picture elements and driving circuits for driving respective picture elements are monolithically formed on an insulating substrate. A protective circuit is provided for allowing input-output terminals of a driving circuit to conduct when a potential difference of not less than a predetermined value is generated. The protective circuit includes an MOS transistor, and a turn-on voltage thereof is set according to a thickness of a gate insulating layer. The protective circuit is formed on the insulating substrate simultaneously when forming the driving circuits. In this arrangement, because the turn-on voltage is set according to the thickness of the gate insulating layer and the thickness can be easily adjusted, an accurate turn-on voltage can be achieved. Since the arrangement prevents an increase in manufacturing cost, the driving circuits, etc., can be surely protected against static electricity generated in the manufacturing process and the input surge in the normal operation.

摘要翻译： 用于驱动各个像素的图像元件和驱动电路单片地形成在绝缘基板上。 提供保护电路，用于当产生不小于预定值的电位差时允许驱动电路的输入输出端子导通。 保护电路包括MOS晶体管，并且其导通电压根据栅绝缘层的厚度设定。 当形成驱动电路时，保护电路同时形成在绝缘基板上。 在这种布置中，由于根据栅极绝缘层的厚度设定导通电压并且可以容易地调节厚度，所以可以实现准确的导通电压。 由于该装置防止制造成本的增加，因此可以可靠地保护驱动电路等，以免在制造过程中产生的静电和正常操作中的输入浪涌。

公开(公告)号：US5926158A

公开(公告)日：1999-07-20

申请号：US610128

申请日：1996-02-29

申请人： Hiroshi Yoneda ,  Kenichi Katoh ,  Yutaka Ishii ,  Yasushi Kubota

发明人： Hiroshi Yoneda ,  Kenichi Katoh ,  Yutaka Ishii ,  Yasushi Kubota

IPC分类号： G02F1/133 ,  G02F1/136 ,  G02F1/1368 ,  G09G3/20 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3648 ,  G09G3/3659 ,  G09G2300/0809 ,  G09G2300/0842 ,  G09G2310/0251 ,  G09G2330/023 ,  G09G3/2011

摘要： An active matrix type image display apparatus which includes: a plurality of data signal lines; a plurality of scanning signal lines crossing the plurality of data signal lines; and a plurality of pixel portions disposed in a matrix in areas enclosed by the plurality of data signal lines and the plurality of scanning signal lines, wherein each of the plurality of pixel portions includes: a pixel capacitor for storing electric charge supplied from at least one of the plurality of data signal lines, to display an image; storage unit connected to the pixel capacitor; and switching unit which alternately selects one of an operation for electrically connecting the pixel capacitor to the storage unit and an operation for electrically disconnecting the pixel capacitor from the storage unit.

摘要翻译： 一种有源矩阵型图像显示装置，包括：多条数据信号线; 与所述多条数据信号线交叉的多条扫描信号线; 以及由多个数据信号线和多条扫描信号线包围的区域中矩阵地配置的多个像素部，其中，所述多个像素部分中的每一个包括：像素电容器，用于存储从至少一个 的多个数据信号线，以显示图像; 存储单元连接到像素电容器; 以及切换单元，其交替地选择用于将像素电容器电连接到存储单元的操作中的一个以及用于将像素电容器与存储单元电气断开的操作。

公开(公告)号：US5540550A

公开(公告)日：1996-07-30

申请号：US346688

申请日：1994-11-30

申请人： Yasushi Kubota

发明人： Yasushi Kubota

IPC分类号： F04D29/22

CPC分类号： F04D29/2277 ,  F04D29/2255

摘要： A solid impeller is disclosed having a disk-shaped impeller body having an inlet section extending along the impeller axis of rotation. A plurality of discharge passages extend radially and having inlet and discharge ports. The inlet port has an opening verge face which is oblique to the rotational axis. The solid impeller may also comprise a disk-shaped impeller body having an inlet section extending along the axis of rotation of the impeller and plural discharge passages extending radially. It further has inlet and discharge ports which have a tapered shape so that the section area of the discharge passage is gradually reduced in the outward direction. The thickness of the body is also gradually reduced in the outward direction. The solid impeller may also comprise a cylindrically-shaped center body and plural arms on a peripheral surface of the body. These extend radially in an outward direction from the body and include a discharge passage which extends along a longitudinal direction of the arm.

摘要翻译： 公开了一种固体叶轮，其具有盘形叶轮本体，其具有沿着叶轮转动轴线延伸的入口部分。 多个排放通道径向延伸并具有入口和排出口。 入口具有与旋转轴线倾斜的开口边缘面。 固体叶轮还可以包括具有沿着叶轮的旋转轴线延伸的入口部分的多个圆盘形叶轮本体，并且径向延伸的多个排出通道。 还具有入口排出口，其具有锥形形状，使得排出通道的截面积在向外方向上逐渐减小。 身体的厚度也在向外的方向上逐渐减小。 固体叶轮还可以包括圆柱形中心体和位于主体的外周表面上的多个臂。 它们从主体沿向外的方向径向地延伸并且包括沿着臂的纵向方向延伸的排放通道。

公开(公告)号：US07741985B2

公开(公告)日：2010-06-22

申请号：US11793522

申请日：2006-01-11

申请人： Yasushi Kubota ,  Kazuhiro Maeda ,  Hajime Washio ,  Patrick Zebedee

发明人： Yasushi Kubota ,  Kazuhiro Maeda ,  Hajime Washio ,  Patrick Zebedee

IPC分类号： H03M1/66

CPC分类号： H03M1/802

摘要： A digital/analogue converter for converting an input n-bit digital code, where n is an integer greater than one, has an n-bit digital input and an output for connection to a load, and includes: an array of (n−1) switched capacitors; and a switching arrangement. In one example embodiment, the switching arrangement is adapted, in a zeroing phase of operation, to connect a first reference voltage to the first plate of at least one capacitor of the array and to connect a second plate of the at least one capacitor to a voltage that, for at least one value of the input digital code, is different from the first reference voltage and is further adapted, in a decoding phase of operation, to enable, dependent on the value of the input digital code, injection of charge into the at least one capacitor. In one example embodiment, the converter may be a bufferless converter having an output for direct connection to a capacitive load.

摘要翻译： 一种数字/模拟转换器，用于转换其中n是大于1的整数的输入n位数字码，具有n位数字输入和用于连接到负载的输出，并且包括：（n-1） ）开关电容器; 和切换装置。 在一个示例性实施例中，切换装置在操作的归零阶段适于将第一参考电压连接到阵列的至少一个电容器的第一板，并将至少一个电容器的第二板连接到 电压，对于输入数字代码的至少一个值，与第一参考电压不同，并且在操作的解码阶段中进一步适应于使得能够依赖于输入数字代码的值将电荷注入 所述至少一个电容器。 在一个示例性实施例中，转换器可以是具有用于直接连接到电容性负载的输出的无缓冲转换器。

公开(公告)号：US07663613B2

公开(公告)日：2010-02-16

申请号：US10159288

申请日：2002-06-03

申请人： Yukio Tanaka ,  Munehiro Azami ,  Yasushi Kubota ,  Hajime Washio

发明人： Yukio Tanaka ,  Munehiro Azami ,  Yasushi Kubota ,  Hajime Washio

IPC分类号： G09G5/00 ,  G06F3/038

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2310/0297

摘要： An occupying area of a digital system signal line driver circuit in an image display device is large and this hinders the miniaturization of the display device. A memory circuit and a D/A converter circuit in the signal line driver circuit are commonly used for n (“n” is a natural number equal to or larger than 2) signal lines. One horizontal scanning period is divided into n periods and the memory circuit and the D/A converter circuit each perform processing for different signal lines during each of the divided periods. Thus, all the signal lines can be driven. Therefore, the number of memory circuits and the number of D/A converter circuits in the signal line driver circuit can be reduced to one n-th in a conventional case.

摘要翻译： 图像显示装置中的数字系统信号线驱动电路的占有面积大，妨碍显示装置的小型化。 信号线驱动电路中的存储电路和D / A转换电路通常用于n（“n”是等于或大于2的自然数）的信号线。 一个水平扫描周期被分为n个周期，并且存储器电路和D / A转换器电路在每个分割周期期间各自执行不同信号线的处理。 因此，可以驱动所有的信号线。 因此，在常规情况下，信号线驱动电路中的存储电路数量和D / A转换电路的数量可以减少到1 / n。

公开(公告)号：US07196699B1

公开(公告)日：2007-03-27

申请号：US09506033

申请日：2000-02-16

申请人： Yasushi Kubota ,  Hajime Washio ,  Ichiro Shiraki ,  Kazuhiro Maeda ,  Yasuyoshi Kaise

发明人： Yasushi Kubota ,  Hajime Washio ,  Ichiro Shiraki ,  Kazuhiro Maeda ,  Yasuyoshi Kaise

IPC分类号： G09G5/00 ,  G09G3/26 ,  H03K19/0175 ,  H03K19/00 ,  H03K5/153

CPC分类号： G09G3/3677 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/021 ,  G09G2310/0289 ,  G09G2330/021 ,  G11C19/00 ,  G11C19/28

摘要： A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.

摘要翻译： CMOS逻辑电路包括两个电流路径，每个电路具有由n型和p型晶体管组成的电路。 在由n型或p型晶体管组成的电路中，一个电流路径设置有与具有CMOS逻辑电路的n型晶体管的电路相同结构的电路，该逻辑电路输出类似于 该逻辑电路的另一个电流路径具有与具有CMOS逻辑电路的p型晶体管的电路相同结构的电路，该电路输出类似于该逻辑电路的逻辑运算结果。 在由另一沟道型构成的另一电路中，设置在一个电流路径上的晶体管的栅电极和设置在另一电流路径上的晶体管的栅电极连接到对应物的漏电极。 根据该结构，可以使输入信号的幅度小于逻辑电路的电源电压。

公开(公告)号：US07079096B2

公开(公告)日：2006-07-18

申请号：US10253570

申请日：2002-09-24

申请人： Hajime Washio ,  Yasuyoshi Kaise ,  Kazuhiro Maeda ,  Yasushi Kubota

发明人： Hajime Washio ,  Yasuyoshi Kaise ,  Kazuhiro Maeda ,  Yasushi Kubota

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2310/0248

摘要： Before a potential of counter electrode is changed, a potential holding circuit fixedly holds potentials of data signal lines S during a non-selective period of scanning signal lines G. This prevents the potentials of the data signal lines S from being an undesirably large potential, which is caused by coupling capacitors between the counter electrode and each data signal line S, whereby it is possible to supply to the pixel capacitor an electric charge corresponding to a gradation to be displayed, by using the relatively low potentials of the data signal lines S. This lowers a power supply voltage of a data signal driving circuit SD, thus reducing the electric power consumption. In short, with this arrangement, a liquid crystal display device can perform an opposed AC drive for line-inversion drive, frame-inversion drive and the like, by low power supply voltage of the data signal line driving circuit SD, thereby reducing the electric power consumption.

公开(公告)号：US07071912B2

公开(公告)日：2006-07-04

申请号：US10631731

申请日：2003-08-01

申请人： Hongyong Zhang ,  Yosuke Tsukamoto ,  Yutaka Takafuji ,  Yasushi Kubota

发明人： Hongyong Zhang ,  Yosuke Tsukamoto ,  Yutaka Takafuji ,  Yasushi Kubota

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3677

摘要： A display panel drive circuit and a display panel are provided which are simple in structure but free from initial failure leading to impossibility to perform scanning. The display panel drive circuit of the present invention is structured such that thin film transistors constituting a signal input circuit connected to a circuit outside the display panel are formed in a structure having a dielectric breakdown strength higher than those of thin film transistors constituting other circuits. Specifically, countermeasures are taken by transistor formation in multi-gate structure, gate width broadening, resistance insertion between an input terminal and a transistor or the like. In the present invention, the circuit to which signals are externally inputted or thin film transistors of the same circuit is structured to withstand high voltage, thereby preventing the transistors from being deteriorated by high voltage and occurrence of initial failure while being simple in structure.

公开(公告)号：US06940500B2

公开(公告)日：2005-09-06

申请号：US10252497

申请日：2002-09-23

申请人： Hajime Washio ,  Yasuyoshi Kaise ,  Kazuhiro Maeda ,  Yasushi Kubota

发明人： Hajime Washio ,  Yasuyoshi Kaise ,  Kazuhiro Maeda ,  Yasushi Kubota

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G09G5/00

CPC分类号： G09G3/3648 ,  G09G3/3688 ,  G09G2310/0248 ,  G09G2330/021

摘要： A potential of a data signal line S during a scanning period is charged to a substantially intermediate potential of a data signal at a corresponding frame. Thus, extremely large dispersion does not occur in a potential of each pixel capacitor with respect to a potential of the data signal line S, so that it is possible to restrict dispersion of a leak current flowing via an active element of each pixel. Thus, potential variation of a pixel PIX is reduced, so that it is possible to improve display quality during a non-scanning period. That is, in an active-matrix-type liquid crystal display, when a frame frequency is reduced by setting the non-scanning period to be sufficiently larger than a scanning period while a standby image is being displayed so as to realize low power consumption, the display quality is improved.

摘要翻译： 扫描周期期间的数据信号线S的电位被充电到相应帧的数据信号的大致中间电位。 因此，相对于数据信号线S的电位，每个像素电容器的电位不会发生极大的色散，从而可以限制流过每个像素的有源元件的漏电流的色散。 因此，像素PIX的电位变化减小，使得可以在非扫描期间提高显示质量。 也就是说，在有源矩阵型液晶显示器中，当通过在显示待机图像的同时将非扫描周期设置为比扫描周期充分大来降低帧频，从而实现低功耗， 显示质量得到提高。