公开(公告)号：US07064982B2

公开(公告)日：2006-06-20

申请号：US10844562

申请日：2004-05-13

申请人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C16/04

CPC分类号： H01L29/792 ,  G11C16/0408 ,  H01L21/28282

摘要： A semiconductor memory device includes a memory cell including a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges; a switching transistor circuit including a negative voltage switching circuit for applying a negative voltage to the gate electrode of the memory cell, and a switching transistor connected to an output of the negative voltage switching circuit and a first voltage source for outputting a voltage having a voltage level lower than zero volt; a pull-up circuit connected to a control terminal of the switching transistor and selectively connected to a second voltage source for outputting a voltage having a voltage level higher than zero volt; and a pull-down circuit connected to the first voltage source and the control terminal of the switching transistor.

摘要翻译： 一种半导体存储器件包括：存储单元，包括通过栅极绝缘膜形成在半导体层上的栅极电极，设置在栅极电极下方的沟道区域，设置在沟道区域两侧的扩散区域，并且具有与该沟道区域相反的导电类型 以及形成在栅电极的两侧并具有保持电荷的功能的存储功能单元; 开关晶体管电路，包括用于向存储单元的栅电极施加负电压的负电压切换电路，以及连接到负电压开关电路的输出的开关晶体管和用于输出具有电压的电压的第一电压源 电平低于零伏; 连接到所述开关晶体管的控制端子并且选择性地连接到用于输出具有高于零伏的电压电平的电压的第二电压源的上拉电路; 以及连接到开关晶体管的第一电压源和控制端子的下拉电路。

公开(公告)号：US06862251B2

公开(公告)日：2005-03-01

申请号：US10847304

申请日：2004-05-18

申请人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C16/06 ,  G11C5/00 ,  G11C8/00 ,  G11C11/22 ,  G11C16/02 ,  G11C16/04 ,  G11C16/08 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/08 ,  G11C11/22 ,  G11C16/0475 ,  H01L21/28282 ,  H01L21/28291 ,  H01L29/42332 ,  H01L29/66833 ,  H01L29/6684 ,  H01L29/7887

摘要： A semiconductor memory device includes a first nonvolatile memory cell, a bit line connected to the first nonvolatile memory cell, and a control circuit connected to the first nonvolatile memory cell and the bit line, and disposed and configured in such a manner as to reset the bit line to a predetermined first potential state only for a certain period “a” of time in response to transition of an input address signal. The first nonvolatile memory cell has a gate electrode formed on a semiconductor layer via a gate insulating film; a channel region disposed under the gate electrode; diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region; and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.

摘要翻译： 半导体存储器件包括第一非易失性存储器单元，连接到第一非易失性存储器单元的位线和连接到第一非易失性存储单元和位线的控制电路，并且被配置和配置为使复位 位线到达预定的第一电位状态，仅响应于输入地址信号的转变而在一定时间段“a”。 第一非易失性存储单元具有通过栅极绝缘膜形成在半导体层上的栅电极; 设置在所述栅电极下方的沟道区域; 扩散区域设置在沟道区域的两侧并且具有与沟道区域的导电类型相反的导电类型; 以及形成在栅电极的两侧并具有保持电荷的功能的存储功能单元。

公开(公告)号：US07372758B2

公开(公告)日：2008-05-13

申请号：US10529880

申请日：2003-10-02

申请人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Kei Tokui ,  Masaru Nawaki

发明人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Kei Tokui ,  Masaru Nawaki

IPC分类号： G11C7/00

CPC分类号： H01L21/28273 ,  G11C16/225 ,  H01L29/7887

摘要： A memory cell array employs a memory element as a memory cell. The memory element is constructed of a gate electrode formed via a gate insulation film on a semiconductor layer, a channel region arranged under the gate electrode, diffusion regions that are arranged on both sides of the channel region and have a conductive type opposite to that of the channel region, and memory function bodies that are arranged on both sides of the gate electrode and have a function to retain electric charges. When first and second power voltages VCC1 and VCC2 supplied from the outside are lower than a prescribed voltage, a rewrite command to a memory circuit 34 that includes the memory cell array is inhibited by a lockout circuit 33a. With this arrangement, there are provided a semiconductor storage device capable of achieving storage retainment of two bits or more per memory element and stable operation even if the device is miniaturized and preventing the occurrence of a malfunction of rewrite error and so on attributed to a reduction in the power voltage supplied from the outside and a control method therefor.

摘要翻译： 存储单元阵列采用存储元件作为存储单元。 存储元件由在半导体层上形成的栅极绝缘膜，配置在栅电极下方的沟道区域形成的栅极电极构成，扩散区域配置在沟道区域的两侧，具有与 沟道区域和存储器功能体，其布置在栅电极的两侧并具有保持电荷的功能。 当从外部提供的第一和第二电源电压VCC 1和VCC 2低于规定电压时，由锁存电路33a禁止包括存储单元阵列的存储电路34的重写命令。 通过这种布置，提供了一种半导体存储装置，其能够实现每个存储元件的两位或更多的存储保持和稳定的操作，即使该装置小型化并且防止归因于减少的重写错误等的故障的发生 在外部提供的电源电压及其控制方法中。

公开(公告)号：US07038282B2

公开(公告)日：2006-05-02

申请号：US10770627

申请日：2004-02-04

申请人： Kei Tokui ,  Hiroshi Iwata ,  Yoshifumi Yaoi ,  Akihide Shibata ,  Masaru Nawaki

发明人： Kei Tokui ,  Hiroshi Iwata ,  Yoshifumi Yaoi ,  Akihide Shibata ,  Masaru Nawaki

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792 ,  H01L29/7923

摘要： A semiconductor storage device includes a voltage supply circuit generating a voltage of 5V, a voltage polarity inversion circuit generating a voltage of −5V, a select-and-connect circuit supplying the voltages of 5V and −5V to a memory cell array, a 5 V voltage level detection circuit detecting the voltage derived from the voltage supply circuit, and a −5 V voltage level detection circuit detecting the voltage derived from the voltage polarity inversion circuit. Absolute values of the voltages detected by the voltage level detection circuits are lower than ever before. This allows a gate insulation film to be thinner. A memory-function film is formed on both sides of a gate electrode in the semiconductor storage device. This also make the gate insulation film thinner. The thin gate insulation film suppresses the short-channel effect, so that each memory element of the memory cell array is miniaturized.

摘要翻译： 半导体存储装置包括产生5V电压的电压供给电路，产生-5V的电压的电压极性反转电路，向存储单元阵列供给5V和-5V的电压的选择和连接电路，5 V电压检测电路，检测从电压供给电路得到的电压;以及-5V电压电平检测电路，检测从电压极性反转电路得到的电压。 由电压电平检测电路检测到的电压的绝对值比以前低。 这允许栅极绝缘膜更薄。 存储功能膜形成在半导体存储装置中的栅电极的两侧。 这也使栅极绝缘膜更薄。 薄栅绝缘膜抑制短沟道效应，使得存储单元阵列的每个存储元件小型化。

公开(公告)号：US07203118B2

公开(公告)日：2007-04-10

申请号：US10528997

申请日：2003-09-10

申请人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Masaru Nawaki ,  Kei Tokui

发明人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Masaru Nawaki ,  Kei Tokui

IPC分类号： G11C5/14

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/7887

摘要： When an input voltage determining circuit 24 determines that an input voltage exceeds a prescribed voltage, a control circuit 25 of a positive polarity power selector circuit 22 turns on a first switch SW1 and turns off second and third switches SW2 and SW3, thereby supplying the input voltage to a memory cell array 21 via the first switch SW1. When the input voltage determining circuit 24 determines that the input voltage is not higher than the prescribed voltage, the control circuit 25 turns off the first switch SW1 and turns on the second and third switches SW2 and SW3, thereby supplying a voltage from a charge pump 23 via the second and third switches SW2 and SW3. By this operation, the memory element is able to retain storage of two bits or more even if miniaturized, to execute stable operation with a small circuit area and to prevent circuit malfunction attributed to a small current supplied to the memory cell array.

摘要翻译： 当输入电压确定电路24确定输入电压超过规定电压时，正极性功率选择电路22的控制电路25接通第一开关SW 1并关断第二和第三开关SW 2和SW 3，由此 通过第一开关SW 1将输入电压提供给存储单元阵列21。 当输入电压确定电路24确定输入电压不高于规定电压时，控制电路25关闭第一开关SW 1并接通第二和第三开关SW 2和SW 3，从而提供来自 经由第二和第三开关SW 2和SW 3的电荷泵23。 通过该操作，即使小型化，存储元件也能够保持两位以上的存储，能够以较小的电路面积进行稳定的动作，并且防止归因于提供给存储单元阵列的小电流引起的电路故障。

公开(公告)号：US20060109729A1

公开(公告)日：2006-05-25

申请号：US10528997

申请日：2003-09-10

申请人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Masaru Nawaki ,  Kei Tokui

发明人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Masaru Nawaki ,  Kei Tokui

IPC分类号： G11C5/14

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/7887

摘要： When an input voltage determining circuit 24 determines that an input voltage exceeds a prescribed voltage, a control circuit 25 of a positive polarity power selector circuit 22 turns on a first switch SW1 and turns off second and third switches SW2 and SW3, thereby supplying the input voltage to a memory cell array 21 via the first switch SW1. When the input voltage determining circuit 24 determines that the input voltage is not higher than the prescribed voltage, the control circuit 25 turns off the first switch SW1 and turns on the second and third switches SW2 and SW3, thereby supplying a voltage from a charge pump 23 via the second and third switches SW2 and SW3. By this operation, the memory element is able to retain storage of two bits or more even if miniaturized, to execute stable operation with a small circuit area and to prevent circuit malfunction attributed to a small current supplied to the memory cell array.

摘要翻译： 当输入电压确定电路24确定输入电压超过规定电压时，正极性功率选择电路22的控制电路25接通第一开关SW 1并关断第二和第三开关SW 2和SW 3，由此 通过第一开关SW 1将输入电压提供给存储单元阵列21。 当输入电压确定电路24确定输入电压不高于规定电压时，控制电路25关断第一开关SW 1并接通第二和第三开关SW 2和SW 3，从而提供来自 经由第二和第三开关SW 2和SW 3的电荷泵23。 通过该操作，即使小型化，存储元件也能够保持两位以上的存储，能够以较小的电路面积进行稳定的动作，并且防止归因于提供给存储单元阵列的小电流引起的电路故障。

公开(公告)号：US20060244049A1

公开(公告)日：2006-11-02

申请号：US10529880

申请日：2003-10-02

申请人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Kei Tokui ,  Masaru Nawaki

发明人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Kei Tokui ,  Masaru Nawaki

IPC分类号： H01L29/792

CPC分类号： H01L21/28273 ,  G11C16/225 ,  H01L29/7887

摘要： A memory cell array employs a memory element as a memory cell. The memory element is constructed of a gate electrode formed via a gate insulation film on a semiconductor layer, a channel region arranged under the gate electrode, diffusion regions that are arranged on both sides of the channel region and have a conductive type opposite to that of the channel region, and memory function bodies that are arranged on both sides of the gate electrode and have a function to retain electric charges. When first and second power voltages VCC1 and VCC2 supplied from the outside are lower than a prescribed voltage, a rewrite command to a memory circuit 34 that includes the memory cell array is inhibited by a lockout circuit 33a. With this arrangement, there are provided a semiconductor storage device capable of achieving storage retainment of two bits or more per memory element and stable operation even if the device is miniaturized and preventing the occurrence of a malfunction of rewrite error and so on attributed to a reduction in the power voltage supplied from the outside and a control method therefor.

摘要翻译： 存储单元阵列采用存储元件作为存储单元。 存储元件由在半导体层上形成的栅极绝缘膜，配置在栅电极下方的沟道区域形成的栅极电极构成，扩散区域配置在沟道区域的两侧，具有与 沟道区域和存储器功能体，其布置在栅电极的两侧并具有保持电荷的功能。 当从外部提供的第一和第二电源电压VCC 1和VCC 2低于规定电压时，由锁存电路33a禁止包括存储单元阵列的存储电路34的重写命令。 通过这种布置，提供了一种半导体存储装置，其能够实现每个存储元件的两位或更多的存储保持和稳定的操作，即使该装置小型化并且防止归因于减少的重写错误等的故障的发生 在外部提供的电源电压及其控制方法中。

公开(公告)号：US06985397B2

公开(公告)日：2006-01-10

申请号：US10808581

申请日：2004-03-25

申请人： Kei Tokui ,  Hiroshi Iwata ,  Yoshifumi Yaoi ,  Akihide Shibata ,  Masaru Nawaki

发明人： Kei Tokui ,  Hiroshi Iwata ,  Yoshifumi Yaoi ,  Akihide Shibata ,  Masaru Nawaki

IPC分类号： G11C7/00 ,  G11C16/04

CPC分类号： G11C16/30

摘要： A semiconductor storage device has a variable-stage charge pump, and a memory cell array to which an output from an output line of the variable-stage charge pump is fed. In the variable-stage charge pump, first and second charge pumps are connected in parallel between a common input bus and a common output bus. A first n-channel MOSFET is provided on a line connecting an output terminal of the first charge pump and the common output bus, and another n-channel MOSFET is provided on a line connecting the second charge pump and the common output bus. First switches are provided between the output terminal of the first charge pump and the first n-channel MOSFET, and between the input terminal of the second charge pump and the second switch. A second switch is provided on a line connecting an input terminal of the second charge pump and the common input bus.

摘要翻译： 半导体存储装置具有可变级电荷泵以及来自可变级电荷泵的输出线的输出的存储单元阵列。 在可变级电荷泵中，第一和第二电荷泵在公共输入总线和公共输出总线之间并联连接。 在连接第一电荷泵的输出端和公共输出总线的线路上设置第一n沟道MOSFET，并且在连接第二电荷泵和公共输出总线的线路上提供另一n沟道MOSFET。 第一开关设置在第一电荷泵的输出端和第一n沟道MOSFET之间，以及第二电荷泵的输入端和第二开关之间。 在连接第二电荷泵的输入端和公共输入总线的线路上设置有第二开关。

公开(公告)号：US07116579B2

公开(公告)日：2006-10-03

申请号：US10851517

申请日：2004-05-20

申请人： Yoshinao Morikawa ,  Masaru Nawaki ,  Hiroshi Iwata ,  Akihide Shibata

发明人： Yoshinao Morikawa ,  Masaru Nawaki ,  Hiroshi Iwata ,  Akihide Shibata

IPC分类号： G11C11/34

CPC分类号： G11C16/0475

摘要： A semiconductor storage device is provided, which comprises a memory array comprising memory elements, a write state machine for performing a sequence of a program or erase operation with respect to the memory array, a decoder for decoding a signal indicating a current state of the write state machine, which is output from the write state machine, and outputting a status signal indicating a status of the program or erase operation with respect to the memory array, a status register for storing the status signal, and an output circuit for outputting the status signal stored in the status register. Each memory element comprises a gate electrode, a channel region, diffusion regions, and memory function sections provided on opposite sides of the gate electrode and having a function of retaining charges.

摘要翻译： 提供了一种半导体存储装置，其包括存储器阵列，其包括存储器元件，用于执行关于存储器阵列的编程或擦除操作序列的写入状态机，用于对指示写入的当前状态的信号进行解码的解码器 状态机，其从写入状态机输出，并且输出指示关于存储器阵列的编程或擦除操作的状态的状态信号，用于存储状态信号的状态寄存器，以及用于输出状态的输出电路 信号存储在状态寄存器中。 每个存储元件包括栅电极，沟道区，扩散区和设置在栅电极的相对侧上并具有保持电荷的功能的存储功能部。

公开(公告)号：US06982906B2

公开(公告)日：2006-01-03

申请号：US10841688

申请日：2004-05-06

申请人： Nobuaki Matsuoka ,  Masaru Nawaki ,  Yoshinao Morikawa ,  Hiroshi Iwata ,  Akihide Shibata

发明人： Nobuaki Matsuoka ,  Masaru Nawaki ,  Yoshinao Morikawa ,  Hiroshi Iwata ,  Akihide Shibata

IPC分类号： G11C16/06

CPC分类号： H01L29/7923 ,  G11C16/3454 ,  H01L21/28282

摘要： A semiconductor memory device of the present invention includes an electrically programmable and erasable nonvolatile memory device which uses a plurality of memory cells requiring a first potential for reading data and a second potential for data programming, the second potential being higher than the first potential, a latch circuit for receiving data and temporarily storing the data, a pulse generator which generates a pulse used for programming data into a memory cell and is coupled in order to receive the second potential, a comparator for comparing data in the latch circuit with data in a memory cell, and a controller for controlling the pulse generator to repeatedly generate a pulse until the data in the latch circuit matches the data in the memory cell, the controller coupled to the comparator and the pulse generator. The controller controls so that the pulse is repeatedly generated until data is programmed in a memory cell. It is thereby possible to improve the speed of writing and erasing processes on a nonvolatile memory cell of the present invention and to improve reliability.

摘要翻译： 本发明的半导体存储器件包括电可编程和可擦除的非易失性存储器件，其使用需要第一电位读取数据的多个存储器单元和用于数据编程的第二电位，第二电位高于第一电位，a 锁存电路，用于接收数据和临时存储数据;脉冲发生器，其生成用于将数据编程到存储器单元中并被耦合以便接收第二电位的脉冲;比较器，用于将锁存电路中的数据与 存储单元和控制器，用于控制脉冲发生器重复产生脉冲，直到锁存电路中的数据与存储单元中的数据匹配，该控制器耦合到比较器和脉冲发生器。 控制器控制，使脉冲重复生成，直到数据被编程到存储单元中。 由此，能够提高本发明的非易失性存储单元的写入和擦除处理速度，提高可靠性。