公开(公告)号：US20100307713A1

公开(公告)日：2010-12-09

申请号：US12745399

申请日：2008-11-05

申请人： Toshiaki Ito ,  Noboru Kubota ,  Kazumi Touno

发明人： Toshiaki Ito ,  Noboru Kubota ,  Kazumi Touno

IPC分类号： B22D11/06 ,  B22D11/16 ,  B22D11/124

CPC分类号： B22D11/0605 ,  B22D11/0677 ,  B22D11/0685

摘要： There is provided a twin-belt casting machine which prevents an uneven cooling condition between the top surface and the bottom surface of a slab between a pair of endless belts disposed vertically. The twin-belt casting machine 1 comprises a pair of rotating belt units 3 including respective endless belts 2 and arranged up and down so as to face each other, a cavity 4 formed between the pair of rotating belt units 3, and cooling means 10 which is arranged inside the rotating belt unit 3. The twin-belt casting machine 1 continuously casts a slab S as a metal liquid is supplied in the cavity 4. The twin-belt casting machine 1 further comprises distance adjusting means which is arranged inside at least one of the pair of rotating belt units arranged up and down so as to face each other, and which moves apart or closer the endless belt relative to the slab S in accordance with a part where the slab and the endless belt become distant from each other.

摘要翻译： 提供一种双带铸造机，其防止在垂直布置的一对环形带之间的板坯的顶表面和底表面之间的不均匀冷却状态。 双带铸造机1包括一对旋转带单元3，其包括相应的环形带2并且彼此相对地上下设置，形成在一对旋转带单元3之间的空腔4和冷却装置10， 布置在旋转带单元3的内部。双带铸造机1连续铸造作为金属液体的板坯S而被供应到空腔4中。双带铸造机1还包括距离调节装置，其至少布置在内部 一对旋转带单元中的一对旋转带单元被布置成彼此面对，并且根据板坯和环形带彼此远离的部分使环形带相对于板坯S分开或更靠近 。

公开(公告)号：US07821076B2

公开(公告)日：2010-10-26

申请号：US12422278

申请日：2009-04-12

申请人： Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

发明人： Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/62

CPC分类号： H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L2224/05554

摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

摘要翻译： 提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。 在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。 形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。 每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

公开(公告)号：US07512917B2

公开(公告)日：2009-03-31

申请号：US11360617

申请日：2006-02-24

申请人： Mikio Izumi ,  Toshifumi Hayashi ,  Shigeru Odanaka ,  Hirotaka Sakai ,  Naotaka Oda ,  Toshifumi Sato ,  Toshiaki Ito

发明人： Mikio Izumi ,  Toshifumi Hayashi ,  Shigeru Odanaka ,  Hirotaka Sakai ,  Naotaka Oda ,  Toshifumi Sato ,  Toshiaki Ito

IPC分类号： G06F17/50

CPC分类号： G06F17/5027

摘要： A verification method is provided for verifying a safety apparatus including a programmable logic device having a plurality of functional elements. The verification method includes the steps of exhaustively verifying the plurality of functional elements on actual hardware, generating a functional element that is the same as one of the functional elements verified on the actual apparatus using a predetermined hardware description language, independently logic-synthesizing each generated functional element into a plurality of first net lists, generating a connection function between the functional elements using the predetermined hardware description language, logic-synthesizing the generated connection function into a second net list corresponding to the connection function, synthesizing the first net lists with the second net list to generate a third net list, writing a logic circuit into the programmable logic device on the basis of the third net list, and verifying the actual programmable logic device.

摘要翻译： 提供了一种用于验证包括具有多个功能元件的可编程逻辑器件的安全装置的验证方法。 验证方法包括以下步骤：在实际硬件上彻底验证多个功能元件，生成与使用预定的硬件描述语言在实际装置上验证的功能元件中的一个功能元件相同的功能元件，独立地逻辑合成每个产生的功能元件 功能元件组合成多个第一网络列表，使用预定的硬件描述语言在功能元件之间生成连接功能，将生成的连接功能逻辑合成到与连接功能相对应的第二网络列表中，将第一网络列表与 第二网络列表以产生第三网络列表，基于第三网络列表将逻辑电路写入可编程逻辑设备，以及验证实际的可编程逻辑设备。

公开(公告)号：US06228421B1

公开(公告)日：2001-05-08

申请号：US09405715

申请日：1999-09-24

申请人： Toshiaki Ito

发明人： Toshiaki Ito

IPC分类号： B05D506

CPC分类号： H01J9/223 ,  C03C17/002 ,  C03C17/004 ,  H01J9/22

摘要： A coating fluid for forming a phosphor screen is coated on an inside surface of a glass panel having a wall portion provided with a wall portion edge at an outside surface of the glass panel. Then, the coating fluid on the inside surface of the glass panel is dried after facing the inside surface of the glass panel downward and placing the wall portion edge onto a panel support stand in a manner that the panel is supported on the support stand primarily by the wall portion edge. Since the glass panel is placed on the support stand in a manner that only the edge portion contacts the support stand, the scattering of coating fluid during this placement can be prevented. As a result, a uniform phosphor layer can be formed on the inside surface of the panel without decreasing the productivity for making such a glass panel on which a phosphor layer is formed.

摘要翻译： 用于形成荧光屏的涂布液涂覆在玻璃面板的内表面上，该玻璃面板具有在玻璃面板的外表面上设置有壁部边缘的壁部。 然后，将玻璃面板的内表面上的涂布液向面对玻璃面板的内侧面进行干燥，将壁部边缘以面板支撑台的方式主要由支撑架 壁部边缘。 由于玻璃面板以只有边缘部分接触支撑架的方式放置在支撑台上，所以可以防止在该放置期间涂布液体的散射。 结果，可以在面板的内表面上形成均匀的荧光体层，而不会降低用于制造其上形成有荧光体层的玻璃面板的生产率。

公开(公告)号：US4762418A

公开(公告)日：1988-08-09

申请号：US70253

申请日：1987-07-06

申请人： Toshiaki Ito ,  Mitsuo Hiramatsu ,  Isuke Hirano

发明人： Toshiaki Ito ,  Mitsuo Hiramatsu ,  Isuke Hirano

IPC分类号： G01J4/00 ,  G01J4/04 ,  G01N21/21

CPC分类号： G01J4/04

摘要： An angle-of-optical-rotation variation measuring apparatus for measuring the highly speedy time-variation of an angle of optical rotation of an optical active substance. The angle-of-optical-rotation variation measuring apparatus comprises an exciting pulse generating source for producing and providing an exciting pulse to a specimen, a light source for providing a monochromatic linearly polarized light beam with the specimen, continuous analysis means for optically rotating the light beam passed through the specimen at successively different angles in the direction of a reference line predetermined to the apparatus and transmitting as an output light beam a part of the light beam which is optically rotated at a predetermined angle, and a streak tube for receiving the output light beam from the analysis means in a direction perpendicular to a time axis of the streak tube.

摘要翻译： 一种用于测量光学活性物质的旋转角度的高度快速时间变化的光轴旋转变化测量装置。 光转角变化测量装置包括用于产生并向样本提供激发脉冲的激励脉冲发生源，用于向样本提供单色线性偏振光束的光源，用于将样品旋转的连续分析装置 光束沿着与设备预定的参考线的方向以连续不同的角度穿过样本，并且作为输出光束传输以预定角度光学旋转的光束的一部分，以及用于接收 在垂直于条纹管的时间轴的方向上从分析装置输出光束。

公开(公告)号：US08110878B2

公开(公告)日：2012-02-07

申请号：US13179163

申请日：2011-07-08

申请人： Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

发明人： Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/62

CPC分类号： H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L2224/05554

摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

摘要翻译： 提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。 在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。 形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。 每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

公开(公告)号：US07982271B2

公开(公告)日：2011-07-19

申请号：US12901858

申请日：2010-10-11

申请人： Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

发明人： Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/62

CPC分类号： H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L2224/05554

摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

摘要翻译： 提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。 在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。 形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。 每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

公开(公告)号：US20090055784A1

公开(公告)日：2009-02-26

申请号：US11360617

申请日：2006-02-24

申请人： Mikio Izumi ,  Toshifumi Hayashi ,  Shigeru Odanaka ,  Hirotaka Sakai ,  Naotaka Oda ,  Toshifumi Sato ,  Toshiaki Ito

发明人： Mikio Izumi ,  Toshifumi Hayashi ,  Shigeru Odanaka ,  Hirotaka Sakai ,  Naotaka Oda ,  Toshifumi Sato ,  Toshiaki Ito

IPC分类号： G06F17/50

CPC分类号： G06F17/5027

摘要： A verification method is provided for verifying a safety apparatus including a programmable logic device having a plurality of functional elements. The verification method includes the steps of exhaustively verifying the plurality of functional elements on actual hardware, generating a functional element that is the same as one of the functional elements verified on the actual apparatus using a predetermined hardware description language, independently logic-synthesizing each generated functional element into a plurality of first net lists, generating a connection function between the functional elements using the predetermined hardware description language, logic-synthesizing the generated connection function into a second net list corresponding to the connection function, synthesizing the first net lists with the second net list to generate a third net list, writing a logic circuit into the programmable logic device on the basis of the third net list, and verifying the actual programmable logic device.

公开(公告)号：US20070185700A1

公开(公告)日：2007-08-09

申请号：US10591433

申请日：2005-03-04

申请人： Mikio Izumi ,  Toshifumi Hayashi ,  Teruji Tarumi ,  Shigeru Odanaka ,  Naotaka Oda ,  Toshiaki Ito ,  Toshifumi Sato ,  Hideyuki Kitazono ,  Tatsuyuki Maekawa

发明人： Mikio Izumi ,  Toshifumi Hayashi ,  Teruji Tarumi ,  Shigeru Odanaka ,  Naotaka Oda ,  Toshiaki Ito ,  Toshifumi Sato ,  Hideyuki Kitazono ,  Tatsuyuki Maekawa

IPC分类号： G06F17/50

CPC分类号： G21D3/04 ,  G21C17/00 ,  G21Y2002/50 ,  G21Y2004/30 ,  G21Y2004/40 ,  Y02E30/39

摘要： A safety protection instrumentation system for a nuclear reactor is constructed by using a digital logic, in which the digital logic includes functional units in which output logic patterns corresponding to all input logic patterns are verified in advance and a functional module formed by combining the functional units.

摘要翻译： 通过使用数字逻辑来构造核反应堆的安全保护仪表系统，其中数字逻辑包括其中预先对与所有输入逻辑模式相对应的输出逻辑模式的功能单元和通过组合功能单元形成的功能模块 。

公开(公告)号：US06818400B2

公开(公告)日：2004-11-16

申请号：US09848771

申请日：2001-05-03

申请人： Toshiaki Ito ,  Kenji Yamamoto ,  Junji Yoshii ,  Atsumi Tsujimoto ,  Hisanori Nasu

发明人： Toshiaki Ito ,  Kenji Yamamoto ,  Junji Yoshii ,  Atsumi Tsujimoto ,  Hisanori Nasu

IPC分类号： C12Q168

CPC分类号： B01J19/0046 ,  B01J2219/00378 ,  B01J2219/00527 ,  B01J2219/00529 ,  B01J2219/00585 ,  B01J2219/00596 ,  B01J2219/00605 ,  B01J2219/00608 ,  B01J2219/00612 ,  B01J2219/00653 ,  B01J2219/00659 ,  B01J2219/00713 ,  B01J2219/00722 ,  C40B40/06 ,  C40B60/14

摘要： The present invention aims at producing a biochip by an inkjet system without wasting a DNA solution. A biochip-producing solution is prepared to contain a combination of a DNA solution 6 to be spotted on a plate 5 and a low-cost buffer solution 7 to be remained in the device after the production. The buffer solution 7 used has a different specific gravity from that of the DNA solution 6 and thus is not mixed therewith.

摘要翻译： 本发明的目的在于通过喷墨系统制造生物芯片而不浪费DNA溶液。制备生物芯片生产溶液，以将待点样的DNA溶液6与低成本缓冲液7组合， 在生产后留在设备中。 所使用的缓冲溶液7与DNA溶液6的比重不同，因此不混合。