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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08482038B2

    公开(公告)日：2013-07-09

    申请号：US13545553

    申请日：2012-07-10

    Applicant: Takayuki Sasaki ,  Yasuto Igarashi ,  Naozumi Morino

    Inventor： Takayuki Sasaki ,  Yasuto Igarashi ,  Naozumi Morino

    IPC: H01L27/118

    CPC classification number: H04B3/32

    Abstract: A technique which reduces the influence of external noise such as crosstalk noise in a semiconductor device to prevent a circuit from malfunctioning. A true signal wire and a bar signal wire which are susceptible to noise and part of an input signal line to a level shifter circuit, and shield wires for shielding these signal wires are laid on an I/O cell. Such I/O cells are placed side by side to complete a true signal wire connection and a bar signal wire connection. These wires are arranged in a way to pass over a plurality of I/O cells and are parallel to each other or multilayered.

    Abstract translation: 减少半导体装置中的串扰噪声等外部噪声的影响的技术，以防止电路发生故障。 易受噪声影响的真实信号线和条形信号线，以及电平移位器电路的输入信号线的一部分以及用于屏蔽这些信号线的屏蔽线布置在I / O单元上。 这样的I / O单元被并排放置以完成真正的信号线连接和条形信号线连接。 这些导线布置成通过多个I / O单元并且彼此平行或多层。

    DATA PROCESSING DEVICE AND MOBILE DEVICE
    2.
    发明申请
    DATA PROCESSING DEVICE AND MOBILE DEVICE 有权
    数据处理设备和移动设备

    公开(公告)号：US20110231694A1

    公开(公告)日：2011-09-22

    申请号：US13152676

    申请日：2011-06-03

    Applicant: KAZUO SAKAMOTO ,  Naozumi Morino ,  Ikuo Kudo

    Inventor： KAZUO SAKAMOTO ,  Naozumi Morino ,  Ikuo Kudo

    IPC: G06F1/04

    CPC classification number: G06F5/06 ,  G06F1/10

    Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.

    Abstract translation: 即使当诸如MMC卡的卡连接到其上时，也提供具有能够正确地锁存数据的存储卡接口的微型计算机。 在具有与诸如存储卡的外部设备的接口的微型计算机中，接口单元设置有连接到外部端子的输出驱动器，用于输出时钟信号以输出时钟信号，并且具有能够传递时钟信号的等效负载电路， 与从时钟信号路径中的输出驱动器之前的级中的任意位置提取的时钟信号相当于连接到外部端子的外部负载引起的延迟的延迟，以便产生用于锁存从外部端子输入的数据的时钟信号 存储卡。

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 失效
    半导体器件

    公开(公告)号：US20090278204A1

    公开(公告)日：2009-11-12

    申请号：US12422278

    申请日：2009-04-12

    Applicant: Naozumi MORINO ,  Atsushi HIRAIWA ,  Kazutoshi OKU ,  Toshiaki ITO ,  Motoshige IGARASHI ,  Takayuki SASAKI ,  Masao SUGIYAMA ,  Hiroshi YANAGITA ,  Shinichi WATARAI

    Inventor： Naozumi MORINO ,  Atsushi HIRAIWA ,  Kazutoshi OKU ,  Toshiaki ITO ,  Motoshige IGARASHI ,  Takayuki SASAKI ,  Masao SUGIYAMA ,  Hiroshi YANAGITA ,  Shinichi WATARAI

    IPC: H01L27/088

    CPC classification number: H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L2224/05554

    Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

    Abstract translation: 提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。 在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。 形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。 每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

    Data processing device and mobile device
    9.
    发明授权
    Data processing device and mobile device 有权

    公开(公告)号：US08572425B2

    公开(公告)日：2013-10-29

    申请号：US13552693

    申请日：2012-07-19

    Applicant: Kazuo Sakamoto ,  Naozumi Morino ,  Ikuo Kudo

    Inventor： Kazuo Sakamoto ,  Naozumi Morino ,  Ikuo Kudo

    IPC: G06F1/04 ,  G06F1/14 ,  G06F1/10

    CPC classification number: G06F5/06 ,  G06F1/10

    Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.

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