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    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20110024847A1

    公开(公告)日：2011-02-03

    申请号：US12901858

    申请日：2010-10-11

    申请人： NAOZUMI MORINO ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

    发明人： NAOZUMI MORINO ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

    IPC分类号： H01L27/092

    CPC分类号： H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L2224/05554

    摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

    摘要翻译： 提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。 在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。 形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。 每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

    Semiconductor device with reduced memory leakage current
    5.
    发明授权
    Semiconductor device with reduced memory leakage current 有权
    具有减少内存泄漏电流的半导体器件

    公开(公告)号：US07095074B2

    公开(公告)日：2006-08-22

    申请号：US10196166

    申请日：2002-07-17

    申请人： Keisuke Tsukamoto ,  Yoshihiro Ikeda ,  Tsutomu Okazaki ,  Daisuke Okada ,  Hiroshi Yanagita

    发明人： Keisuke Tsukamoto ,  Yoshihiro Ikeda ,  Tsutomu Okazaki ,  Daisuke Okada ,  Hiroshi Yanagita

    IPC分类号： H01L29/76 ,  H01L29/788

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11543

    摘要： Defects in element forming regions on which memory cells of a non-volatile memory are formed are to be diminished to reduce leakage current. End portions of element forming regions with non-volatile memory cells formed thereon are extended a length D by utilizing the region which underlies a dummy conductive film, whereby a stress induced from an insulating film which surrounds the element forming regions is concentrated on the extended region. As a result, defects do not extend up to the regions where memory cells are formed and therefore it is possible to reduce leakage current in the memory cells.

    摘要翻译： 在其上形成非易失性存储器的存储单元的元件形成区域中的缺陷将被减小以减少泄漏电流。 在其上形成有非易失性存储单元的元件形成区域的端部通过利用虚设导电膜下面的区域而延伸长度D，由此围绕元件形成区域的绝缘膜引起的应力集中在延伸区域上 。 结果，缺陷不延伸到形成存储单元的区域，因此可以减少存储单元中的漏电流。

    Semiconductor integrated circuit device having a dummy conductive film and method of manufacturing the same
    8.
    发明授权
    Semiconductor integrated circuit device having a dummy conductive film and method of manufacturing the same 有权
    具有虚拟导电膜的半导体集成电路器件及其制造方法

    公开(公告)号：US07001808B2

    公开(公告)日：2006-02-21

    申请号：US10786334

    申请日：2004-02-26

    申请人： Keisuke Tsukamoto ,  Yoshihiro Ikeda ,  Tsutomu Okazaki ,  Daisuke Okada ,  Hiroshi Yanagita

    发明人： Keisuke Tsukamoto ,  Yoshihiro Ikeda ,  Tsutomu Okazaki ,  Daisuke Okada ,  Hiroshi Yanagita

    IPC分类号： H01L31/336

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11543

    摘要： Defects in element forming regions on which memory cells of a non-volatile memory are formed are to be diminished to reduce leakage current. End portions of element forming regions with non-volatile memory cells formed thereon are extended a length D by utilizing the region which underlies a dummy conductive film, whereby a stress induced from an insulating film which surrounds the element forming regions is concentrated on the extended region. As a result, defects do not extend up to the regions where memory cells are formed and therefore it is possible to reduce leakage current in the memory cells.

    摘要翻译： 在其上形成非易失性存储器的存储单元的元件形成区域中的缺陷将被减小以减少泄漏电流。 在其上形成有非易失性存储单元的元件形成区域的端部通过利用虚设导电膜下面的区域而延伸长度D，由此围绕元件形成区域的绝缘膜引起的应力集中在延伸区域上 。 结果，缺陷不延伸到形成存储单元的区域，因此可以减少存储单元中的漏电流。