公开(公告)号：US06351417B1

公开(公告)日：2002-02-26

申请号：US09833687

申请日：2001-04-13

Applicant: Hitoshi Shiga ,  Toru Tanzawa ,  Masanobu Saito

Inventor： Hitoshi Shiga ,  Toru Tanzawa ,  Masanobu Saito

IPC: G11C1616

CPC classification number: G11C16/3409 ,  G11C16/16 ,  G11C16/3404 ,  G11C2216/20

Abstract: A non-volatile semiconductor memory device according to the invention comprises a memory cell array having a plurality of non-volatile memory cells, and a write state machine controlling a voltage applied to a memory cell selected from the memory cell array and a voltage application period, in accordance with each of reading of data from the selected memory cell, writing of data into the selected memory cell, and erasing of data from the selected memory. The write state machine executes writing, under a first writing condition, on a predetermined number of memory cells included in the memory cell array, and executes writing on memory cells other than the predetermined number of memory cells, under a second writing condition set in accordance with a result of the writing executed under the first writing condition.

Abstract translation: 根据本发明的非易失性半导体存储器件包括具有多个非易失性存储单元的存储单元阵列，以及控制施加到从存储单元阵列选择的存储单元的电压的写状态机和施加电压的周期 根据从所选存储单元读取数据的每一个，将数据写入所选存储单元，以及从所选存储器擦除数据。 写入状态机在第一写入条件下执行包含在存储单元阵列中的预定数量的存储单元上的写入，并且在按照相应设置的第二写入条件下执行对除了预定数量的存储单元之外的存储单元的写入 其结果是在第一写入条件下执行写入。

公开(公告)号：US6041012A

公开(公告)日：2000-03-21

申请号：US31686

申请日：1998-02-27

Applicant: Hironori Banba ,  Hitoshi Shiga ,  Shigeru Atsumi ,  Akira Umezawa

Inventor： Hironori Banba ,  Hitoshi Shiga ,  Shigeru Atsumi ,  Akira Umezawa

IPC: G11C5/14 ,  G11C16/30 ,  G11C7/00

CPC classification number: G11C5/143 ,  G11C16/30 ,  G11C5/145 ,  G11C5/147

Abstract: A semiconductor integrated circuit device according to the present invention includes a booster circuit 1 for raising an external power supply voltage Vccext, a level detecting circuit 2 for detecting fluctuation in a stepped-up voltage Vccint2, an internal voltage generating circuit 3 for generating an internal voltage Vccint on the basis of the stepped-up voltage Vccint2, an address buffer 4, an address decoder 5, and a memory cell array 6 of an EEPROM structure. The level detecting circuit 2 includes a first level detecting part for performing level detection during a memory access state, and a second level detecting part for performing level detection during a stand-by state. During the stand-by state, the internal voltage generating circuit 3 short-circuits the stepped-up voltage Vccint2 and the internal voltage Vccint. The second level detecting part has lower power consumption than that of the first level detecting part, so that it is possible to reducing the power consumption during the stand-by state without lowering the driving voltage.

Abstract translation: 根据本发明的半导体集成电路器件包括用于提高外部电源电压Vccext的升压电路1，用于检测升压电压Vccint2中的波动的电平检测电路2，用于产生内部电压的内部电压产生电路3 基于升压电压Vccint2的电压Vccint，地址缓冲器4，地址解码器5和EEPROM结构的存储单元阵列6。 电平检测电路2包括用于在存储器访问状态期间执行电平检测的第一电平检测部分和用于在待机状态期间执行电平检测的第二电平检测部分。 在待机状态下，内部电压产生电路3使升压电压Vccint2和内部电压Vccint短路。 第二电平检测部件具有比第一电平检测部件低的功率消耗，从而可以在不降低驱动电压的情况下降低待机状态下的功耗。

公开(公告)号：US20130246730A1

公开(公告)日：2013-09-19

申请号：US13603697

申请日：2012-09-05

Applicant: Ayako YAMANO ,  Teruo Takagiwa ,  Koichi Fukuda ,  Hitoshi Shiga ,  Osamu Nagao

Inventor： Ayako YAMANO ,  Teruo Takagiwa ,  Koichi Fukuda ,  Hitoshi Shiga ,  Osamu Nagao

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0246 ,  G06F2212/7209 ,  G11C11/5635 ,  G11C16/00 ,  G11C16/16 ,  Y02D10/13

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of blocks in a memory cell, each of the blocks acting as an erasure unit of data, the block including a plurality of pages, each of the pages including a plurality of memory cell transistors, each of the memory cell transistors being configured to be an erasure state or a first retention state based on a threshold voltage of the memory cell transistor, and a controller searching data in the block with respect to, writing a first flag denoting effective into a prescribed page of the block with the erasure state, and writing the first flag denoting non-effective into a prescribed page of the block with the first retention state, reading out the prescribed page of the block with the first retention state, and determining that the block is writable when the first flag denotes effective.

Abstract translation: 根据一个实施例，半导体存储器件包括存储器单元中的多个块，每个块用作数据的擦除单元，该块包括多个页，每个页包括多个存储单元晶体管 每个存储单元晶体管被配置为基于存储单元晶体管的阈值电压的擦除状态或第一保持状态，以及控制器搜索块中的数据，将表示有效的第一标志写入到 具有擦除状态的块的规定页面，并且将表示无效的第一标志写入具有第一保持状态的块的规定页面，以第一保留状态读出块的规定页面，并且确定 当第一个标志表示有效时，块是可写的。

公开(公告)号：US08331158B2

公开(公告)日：2012-12-11

申请号：US13016286

申请日：2011-01-28

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C5/14

CPC classification number: G11C16/10 ,  G11C16/0483

Abstract: In writing operation, charge pumps of a memory apply any of first to n-th voltages which are different from each other. An application-voltage selector selects voltages to be applied to WLs among the first to n-th voltages. A word-line number register stores the number of WLs to which each of the first to n-th voltages is to be applied for the first to n-th voltages. A storage stores a correspondence table that stores a relationship between the number of WLs for each of the first to n-th voltages and the number of charge pumps allocated to the first to n-th voltages. A generation-voltage selector allocates charge pumps to generate the first to n-th voltages based on the correspondence table according to the number of WLs for each of the first to n-th voltages. Each charge pump generates any of the first to n-th voltages allocated by the generation-voltage selector.

Abstract translation: 在写入操作时，存储器的电荷泵应用彼此不同的第一至第n电压中的任何一个。 应用电压选择器选择在第一至第n电压中施加到WL的电压。 字线号寄存器存储要施加第一至第n电压的第一至第n电压中的每一个的WL的数量。 存储器存储存储第一至第n电压中的每一个的WL的数量与分配给第一至第n电压的电荷泵的数量之间的关系的对应表。 发电电压选择器基于与第一至第n电压中的每一个相关的WL的数量的对应表，分配电荷泵以产生第一至第n电压。 每个电荷泵产生由发电电压选择器分配的第一至第n电压中的任一个。

公开(公告)号：US08331147B2

公开(公告)日：2012-12-11

申请号：US12838811

申请日：2010-07-19

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/3436

Abstract: A nonvolatile semiconductor memory device comprises: a memory cell array configured by a plurality of first and second lines and a plurality of memory cells, each of the memory cells being selected by the first and second lines and being configured to store multiple-bit data in a nonvolatile manner; a data bus configured to transmit write data to be written to the plurality of memory cells, the write data being configured by a plurality of unit data; a column selection unit configured by a plurality of data latches, each of the data latches being configured to directly receive the unit data inputted from the data bus and to retain the unit data; and a control unit configured to control activation/non-activation of the data latches. During a programming operation, for each unit data inputted to the column selection unit, the control unit activates one of the data latches corresponding to a certain one of the memory cells where the unit data is to be stored.

Abstract translation: 非易失性半导体存储器件包括：由多个第一和第二线路以及多个存储器单元配置的存储器单元阵列，每个存储单元由第一和第二线路选择，并被配置为存储多位数据 非挥发性; 数据总线，被配置为发送要写入到所述多个存储器单元的写入数据，所述写入数据由多个单位数据配置; 由多个数据锁存器配置的列选择单元，每个数据锁存器被配置为直接接收从数据总线输入的单元数据并保持单元数据; 以及控制单元，被配置为控制数据锁存器的激活/非激活。 在编程操作期间，对于输入到列选择单元的每个单元数据，控制单元激活对应于要存储单元数据的存储单元中的某一个存储单元的数据锁存器之一。

公开(公告)号：US08327063B2

公开(公告)日：2012-12-04

申请号：US12405754

申请日：2009-03-17

Applicant: Hitoshi Shiga ,  Hidetaka Tsuji

Inventor： Hitoshi Shiga ,  Hidetaka Tsuji

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G06F2212/7201

Abstract: A memory system with a semiconductor memory device, in which a physical block of n-bits serves as an erase unit, wherein the address management of the memory device is performed by a logical block with m-bits, “m” being larger than “n” and expressed by a power of two, and wherein a n-bit portion continued from the head address in the logical block is defined as a first management unit corresponding to one physical block of the memory device, and a number of the remaining fraction portions each defined as a second management unit are gathered so as to correspond to one physical block of the memory device.

Abstract translation: 一种具有半导体存储器件的存储器系统，其中n位的物理块用作擦除单元，其中存储器件的地址管理由具有m位的逻辑块执行，m大于n并表示 通过2的幂，并且其中从逻辑块中的头地址继续的n位部分被定义为对应于存储器件的一个物理块的第一管理单元，并且其余的分数部分的数量被定义为 收集第二管理单元以对应于存储器件的一个物理块。

公开(公告)号：US20100241794A1

公开(公告)日：2010-09-23

申请号：US12725519

申请日：2010-03-17

Applicant: Osamu NAGAO ,  Hitoshi Shiga

Inventor： Osamu NAGAO ,  Hitoshi Shiga

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7209

Abstract: A nonvolatile semiconductor memory device according to one aspect of the present invention includes: a memory cell array provided to perform programming in page units; and a control circuit provided to control the programming. The control circuit includes: means that performs a first detection for memory cells in a part provided as a unit smaller than a page, concurrently with programming to memory cells to be written in a page; and means that subjects the memory cells in the page to a second detection that takes into consideration a failure relief due to a redundant region, when the number of memory cells of unwritten state in the part as detected by the first detection becomes equal to or less than a first constant, and that ends the program operation when the number of memory cells of unwritten state in the page becomes equal to or less than a second constant.

Abstract translation: 根据本发明的一个方面的非易失性半导体存储器件包括：设置为以页为单位执行编程的存储单元阵列; 以及设置用于控制编程的控制电路。 控制电路包括：对存储单元进行第一检测的装置，该存储单元在作为小于页面的单位提供的部分中，同时对要写入页面的存储单元进行编程; 并且意味着当第一检测中检测到的部分中未写入状态的存储单元的数目等于或等于或等于或小于第二检测时，考虑到冗余区域引起的故障缓解， 并且当页面中未写入状态的存储单元的数量等于或小于第二常数时，结束程序操作。

公开(公告)号：US07650584B2

公开(公告)日：2010-01-19

申请号：US11838605

申请日：2007-08-14

Applicant: Hitoshi Shiga ,  Kiyofumi Sakurai ,  Kenji Mima

Inventor： Hitoshi Shiga ,  Kiyofumi Sakurai ,  Kenji Mima

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/5077 ,  G11C5/025 ,  H01L27/0207 ,  H01L27/11898

Abstract: An ASIC includes a first-wire extended in a first-direction and a second-wire extended in a parallel direction to the first-wire and both are placed on a first-wire layer; and a third-wire placed on a second-wire layer above the first-wire layer and is extended above the wire and above the second-wire in a second-direction which intersects the first-direction and passing through a first via-hole is connected to the first-wire, and a fourth-wire separated from the third-wire extended in a parallel direction above the first-wire and above the second-wire and a fifth-wire separated from both the third-wire and the fourth-wire and extended in a parallel direction in a smallest space and passing through a second via-hole is connected to the second-wire, wherein, one end of the fifth-wire is extended to the center between the second-wire and the first-wire from above the second-wire.

Abstract translation: ASIC包括沿第一方向延伸的第一线和与第一线并联延伸的第二线，并且两者均放置在第一线层上; 以及放置在所述第一线层上方的二线层上并且在所述线的上方延伸并且在与所述第一方向相交并穿过第一通孔的第二方向上方的所述第二线上的第三线是 连接到第一线，以及与第三线分离的第四线，该第三线在第一线上方平行并且在第二线上方延伸，以及与第三线和第四线分离的第五线， 并且在最小的空间中沿平行方向延伸并穿过第二通孔的第二线连接到第二线，其中，第五线的一端延伸到第二线和第一线之间的中心， 电线从二线以上。

公开(公告)号：US20080043531A1

公开(公告)日：2008-02-21

申请号：US11849891

申请日：2007-09-04

Applicant: Yasushi KAMEDA ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawai

Inventor： Yasushi KAMEDA ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawai

IPC: G11C16/06

CPC classification number: G11C16/102

Abstract: The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.

Abstract translation: 非易失性半导体存储器件具有维持并保持位线的电位的电路，偶数位线或奇数位线中的任一个与电路连接。 当位线电位保持电路连接到偶数位线并执行块复制时，首先将数据输出到偶数位线，并且在确定偶数位线的电位之后，位线电位保持 电路工作。 然后，通过位线电位保持电路来执行偶数位线的电位的偏置，保持并保持位线的电位。 同时，将数据输出到奇数位线，并且确定奇数位线的电位。 然后，将编程电压提供给所选择的字线，并且数据被同时写入（编程）到连接到偶数位线的存储器单元中，并且存储器单元连接到奇数位线。

公开(公告)号：US07193896B2

公开(公告)日：2007-03-20

申请号：US11167301

申请日：2005-06-28

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C29/04 ,  G11C16/06

CPC classification number: G11C11/5642 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2207/2245 ,  G11C2211/5646

Abstract: A semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged to store multi-value data; a sense amplifier circuit configured to read data of and write data in the memory cell array; and a controller configured to control data read and write of the memory cell array, wherein the controller has such a function as, when an upper page data write sequence ends in failure, the upper page data being one to be written into an area of the memory cell array where lower page data has already been written, to cache the lower page data read out of the memory cell array and held in the sense amplifier circuit.

Abstract translation: 半导体存储器件包括：存储单元阵列，其中电可重写和非易失性存储器单元被布置为存储多值数据; 读出放大器电路，被配置为读取存储单元阵列中的数据并写入数据; 以及控制器，其被配置为控制所述存储单元阵列的数据读取和写入，其中所述控制器具有如下功能：当上页数据写入序列以故障结束时，所述上页数据为要写入所述存储单元阵列的区域中的一个 存储单元阵列，其中已经写入较低页数据，以缓存从存储单元阵列读出并保持在读出放大器电路中的下部页数据。