公开(公告)号：US20050164491A1

公开(公告)日：2005-07-28

申请号：US11083782

申请日：2005-03-18

申请人： Hui-Min Mao ,  Yi-Nan Chen

发明人： Hui-Min Mao ,  Yi-Nan Chen

IPC分类号： H01L21/302 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L21/76897 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76895 ,  H01L27/10829 ,  H01L27/10888

摘要： A method of forming a bit line contact hole. After transistors are formed on a substrate, a polysilicon layer conformally covers the transistors and the substrate. The polysilicon layer is defined to form an inner landing pad connecting with a doped region. A passivation layer is formed on the inner landing pad, the transistor and the substrate. An insulating layer with a flat surface is then formed on the passivation layer. A contact opening is formed in the insulating layer and the passivation layer to expose the inner landing pad. M0 etching forms a recess of interconnecting landing pad pattern in the upper portion of the contact opening. M0 deposition is then performed. The formed bit line contact structure comprises a bottom layer of a polysilicon inner landing pad, a contact plug and a top layer of an interconnected landing pad.

摘要翻译： 一种形成位线接触孔的方法。 在晶体管形成在衬底上之后，多晶硅层保形地覆盖晶体管和衬底。 多晶硅层被限定为形成与掺杂区域连接的内部着陆焊盘。 在内层着焊盘，晶体管和衬底上形成钝化层。 然后在钝化层上形成具有平坦表面的绝缘层。 在绝缘层和钝化层中形成接触开口以露出内部着陆焊盘。 M 0蚀刻在接触开口的上部形成互连着陆焊盘图案的凹部。 然后进行M 0沉积。 形成的位线接触结构包括多晶硅内部着陆垫的底层，接触插塞和互连的着陆垫的顶层。

公开(公告)号：US06780739B1

公开(公告)日：2004-08-24

申请号：US10613254

申请日：2003-07-03

申请人： Hui-Min Mao ,  Yi-Nan Chen

发明人： Hui-Min Mao ,  Yi-Nan Chen

IPC分类号： H01L218242

CPC分类号： H01L27/10888 ,  H01L21/76807 ,  H01L21/76895

摘要： A bit line contact structure and method for forming the same. After forming transistors on a substrate, Ti layer, TiN layer and W layer conformally cover the transistors and the substrate. The Ti/TiN/W stacked layer is defined to form an inner landing pad connecting to a source/drain region. A passivation layer is formed on the inner landing pad, the transistors and the substrate. An insulating layer with a flat surface is then formed on the passivation layer. A contact hole is formed in the insulating layer and the passivation layer to expose the inner landing pad. A M0 etching process is performed to form a recess of interconnecting landing pad patterns in the upper portion of the contact hole. An M0 deposition process is then performed.

摘要翻译： 一种位线接触结构及其形成方法。 在衬底上形成晶体管之后，Ti层，TiN层和W层共形覆盖晶体管和衬底。 Ti / TiN / W堆叠层被​​限定为形成连接到源极/漏极区域的内部着陆焊盘。 在内部着陆板，晶体管和基板上形成钝化层。 然后在钝化层上形成具有平坦表面的绝缘层。 在绝缘层和钝化层中形成接触孔以暴露内部着陆焊盘。 执行M0蚀刻工艺以在接触孔的上部形成互连着陆焊盘图案的凹部。 然后执行M0沉积工艺。

公开(公告)号：US07195975B2

公开(公告)日：2007-03-27

申请号：US10714001

申请日：2003-11-14

申请人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hui-Min Mao

发明人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hui-Min Mao

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L21/76897 ,  H01L21/76829 ,  H01L21/76895

摘要： A method of forming a bit line contact via. The method includes providing a substrate having a transistor with a gate electrode, drain region, and source region, forming a conductive layer overlying the drain region, conformally forming an insulating barrier layer overlying the substrate, blanketly forming a dielectric layer overlying the insulating barrier layer, and forming a via through the dielectric layer and insulating barrier layer, exposing the conductive layer.

摘要翻译： 形成位线接触通孔的方法。 该方法包括提供具有晶体管的衬底，该晶体管具有栅极，漏极区和源极区，形成覆盖漏极区的导电层，保形地形成覆盖衬底的绝缘阻挡层，覆盖在绝缘阻挡层上的绝缘层 并且通过介电层和绝缘阻挡层形成通孔，暴露导电层。

公开(公告)号：US07064044B2

公开(公告)日：2006-06-20

申请号：US11019850

申请日：2004-12-21

申请人： Yi-Nan Chen ,  Hui-Min Mao

发明人： Yi-Nan Chen ,  Hui-Min Mao

IPC分类号： H01L21/76

CPC分类号： H01L21/31144 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/76802 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming contact holes using a multi-layer hard mask. A substrate with a device region and an alignment region having an opening therein to serve as an alignment mark is provided. A dielectric layer is formed overlying the substrate and fills the opening, followed by the multi-layer hard mask. The multi-layer hard mask over the opening is partially removed and that on the device region is patterned to form a plurality of holes therein and expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form the plurality of contact holes therein.

摘要翻译： 一种使用多层硬掩模形成接触孔的方法。 提供了具有器件区域和其中具有开口的对准区域用作对准标记的衬底。 形成覆盖在基板上的电介质层，并填充开口，接着是多层硬掩模。 开口上的多层硬掩模被部分去除，并且在器件区域上被图案化以在其中形成多个孔并且暴露下面的介电层。 在器件区域上暴露的介电层被蚀刻以在其中形成多个接触孔。

公开(公告)号：US06987322B2

公开(公告)日：2006-01-17

申请号：US10923591

申请日：2004-08-20

申请人： Yi-Nan Chen ,  Hui-Min Mao

发明人： Yi-Nan Chen ,  Hui-Min Mao

IPC分类号： H01L23/48

CPC分类号： H01L21/31144 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/76802 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming contact holes using a multi-layer hard mask. A substrate with a device region and an alignment region having an opening therein to serve as an alignment mark is provided. A dielectric layer is formed overlying the substrate and fills the opening, followed by the multi-layer hard mask. The multi-layer hard mask over the opening is partially removed and that on the device region is patterned to form a plurality of holes therein and expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form the plurality of contact holes therein.

公开(公告)号：US20050167719A1

公开(公告)日：2005-08-04

申请号：US11068173

申请日：2005-02-28

申请人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

发明人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/10864 ,  H01L27/10867

摘要： A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.

摘要翻译： 具有垂直晶体管和深沟槽电容器的存储器件。 该器件包括含有至少一个深沟槽和沉积在深沟槽的下部的电容器的衬底。 具有第一导电层和第二导电层的导电结构沉积在沟槽电容器上。 环形绝缘体沉积在侧壁上以及衬底和第一导电层之间。 第一导电层被环形绝缘体包围，并且第二导电层沉积在第一导电层和环形绝缘体上。 在深沟槽的侧壁的一侧上沉积第二导电层和深沟槽的衬底之间的扩散阻挡层。 TTO沉积在导电结构上。 控制门被存放在TTO上。

公开(公告)号：US06833081B2

公开(公告)日：2004-12-21

申请号：US10193502

申请日：2002-07-10

申请人： Yi-Nan Chen ,  Hui Min Mao ,  Shih-Chieh Kao ,  Tien-Sung Chen

发明人： Yi-Nan Chen ,  Hui Min Mao ,  Shih-Chieh Kao ,  Tien-Sung Chen

IPC分类号： B08B700

CPC分类号： H01L21/02071 ,  C23G1/125 ,  H01L21/31138 ,  H01L21/32136

摘要： A method of metal etching post cleaning. A substrate with a surface covered by a patterned metal layer and a patterned resist layer in order is provided, subsequently, oxygen-plasma ashing is performed to remove the patterned resist layer to expose the surface of the patterned metal layer. Next, an ozone-plasma ashing is performed to release charges on the surface of the patterned metal layer, the ozone-plasma ashing time at 30 sec˜180 sec, and the ozone-plasma ashing temperature at 200° C.˜300° C. The surface of the patterned metal layer is finally cleaned with sulfuric peroxide, molar concentration of sulfuric acid and hydrogen peroxide therein being 0.07M˜0.4M and 0.8M˜1.5M, respectively. In addition, the temperature of the sulfuric peroxide during post cleaning is 25° C.˜50° C.

摘要翻译： 金属蚀刻后清洗方法。 提供具有被图案化金属层和图案化抗蚀剂层覆盖的表面的衬底，随后执行氧等离子体灰化以去除图案化的抗蚀剂层以暴露图案化金属层的表面。 接下来，进行臭氧等离子体灰化以释放图案化金属层的表面上的电荷，30秒〜180秒的臭氧等离子体灰化时间，以及臭氧等离子体灰化温度在200℃〜300℃ 图案化金属层的表面最后用硫酸过氧化物，硫酸摩尔浓度和过氧化氢分别为0.07M〜0.4M和0.8M〜1.5M。 此外，后清洗时的硫酸过氧化物的温度为25℃〜50℃

公开(公告)号：US08963282B2

公开(公告)日：2015-02-24

申请号：US13231961

申请日：2011-09-14

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/72 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56

CPC分类号： H01L23/562 ,  H01L21/311 ,  H01L21/561 ,  H01L21/76224 ,  H01L21/78 ,  H01L23/3178 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.

摘要翻译： 半导体结构包括矩阵，集成电路和划线。 矩阵包括划线区域和电路区域。 集成电路设置在电路区域内。 划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。 裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

公开(公告)号：US08692245B2

公开(公告)日：2014-04-08

申请号：US13214227

申请日：2011-08-21

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L23/544 ,  H01L23/482 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention in a first aspect proposes a semiconductor structure with a crack stop structure. The semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in the form of a grid to form a crack stop structure.

摘要翻译： 本发明在第一方面提出了一种具有裂纹停止结构的半导体结构。 半导体结构包括矩阵，集成电路和划线。 矩阵包括划线区域和电路区域。 集成电路设置在电路区域内。 划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。 裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

公开(公告)号：US08642479B2

公开(公告)日：2014-02-04

申请号：US13183358

申请日：2011-07-14

申请人： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/302

CPC分类号： H01L21/76802 ,  H01L21/31144 ,  H01L21/32137

摘要： A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O2), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.

摘要翻译： 提供了一种在半导体器件中形成开口的方法，包括：向半导体衬底提供其上顺序形成的氧化硅层，多晶硅层和氮化硅层; 图案化氮化硅层，在氮化硅层中形成第一开口，其中第一开口暴露多晶硅层的顶表面; 使用包括溴化氢（HBr），氧（O 2）和碳氟化合物（C x F y）的气体蚀刻剂进行第一蚀刻工艺，在多晶硅层中形成第二开口，其中与第二开口相邻的多晶硅层的侧壁基本上 垂直于氧化硅层的顶表面，其中x在1-5之间，y在2-8之间; 去除氮化硅层; 以及进行第二蚀刻工艺，在由所述第二开口暴露的所述氧化硅层中形成第三开口。