公开(公告)号：US20090066399A1

公开(公告)日：2009-03-12

申请号：US12230953

申请日：2008-09-09

申请人： An-Tung Chen ,  Li-Wen Fang ,  Hung-Der Su

发明人： An-Tung Chen ,  Li-Wen Fang ,  Hung-Der Su

IPC分类号： H03L5/00

CPC分类号： H03K3/012 ,  H03K3/35613

摘要： A level shift circuit includes an input stage and an output stage coupled to each other by two nodes. The input stage changes the voltages on the nodes according to an input signal, and the output stage determines an output signal according to the voltages on the two nodes. In a transition state, the input stage provides a large current to charge or discharge the first node or the second node so as to quickly change the voltage thereon. In a steady state, the input stage lowers the current so as to reduce power consumption.

摘要翻译： 电平移位电路包括通过两个节点彼此耦合的输入级和输出级。 输入级根据输入信号改变节点上的电压，输出级根据两个节点上的电压来确定输出信号。 在过渡状态下，输入级提供大电流以对第一节点或第二节点进行充电或放电，以便快速地改变其上的电压。 在稳定状态下，输入级降低电流，从而降低功耗。

公开(公告)号：US07382172B2

公开(公告)日：2008-06-03

申请号：US11497587

申请日：2006-08-02

申请人： Pao-Chuan Lin ,  Hung-Der Su ,  An-Tung Chen ,  Jing-Meng Liu

发明人： Pao-Chuan Lin ,  Hung-Der Su ,  An-Tung Chen ,  Jing-Meng Liu

IPC分类号： H03L5/00

CPC分类号： H03K3/35613 ,  H03K3/012

摘要： The present invention discloses a level shift circuit which comprises: level shift means for receiving an input of a first operational voltage and generating an output of a second operational voltage; and a current path connecting with a source of the second operational voltage and providing current to the output of the level shift means to speed up output level switching. The circuit preferably further comprises a power consumption control circuit for stopping excess power consumption when the output of the level shift means has substantially accomplished level switching.

摘要翻译： 本发明公开了一种电平移位电路，包括：电平移位装置，用于接收第一工作电压的输入并产生第二工作电压的输出; 以及与第二工作电压源连接并将电流提供给电平移位装置的输出的电流路径，以加速输出电平切换。 电路优选地还包括功率消耗控制电路，用于在电平移位装置的输出基本上实现电平切换时停止多余的功率消耗。

公开(公告)号：US07327124B2

公开(公告)日：2008-02-05

申请号：US11388158

申请日：2006-03-24

申请人： Jing-Meng Liu ,  Chung-Lung Pai ,  Hung-Der Su ,  Wei-Hsin Wei

发明人： Jing-Meng Liu ,  Chung-Lung Pai ,  Hung-Der Su ,  Wei-Hsin Wei

IPC分类号： G05F1/577

CPC分类号： H02M3/157 ,  H02M3/1588 ,  Y02B70/1466

摘要： A plurality of switches, an inductor and two capacitors are configured to be a boost-inverting converter. To operate the converter in a boost-inverting mode, a control apparatus and method switch the switches such that the inductor is energized in a first phase, the first capacitor is discharged to produce an inverting voltage in a second phase, and the capacitor Cout1 is discharged to produce the inverting voltage and the second capacitor is charged to produce a boost voltage in a third phase. Therefore, the boost-inverting converter has lower peak inductor current and less power loss, and the limitation to the switch design for the boost-inverting converter is relaxed.

摘要翻译： 多个开关，电感器和两个电容器被配置为升压反相转换器。 为了在升压反转模式下操作转换器，控制装置和方法切换开关使得电感器在第一相中通电，第一电容器被放电以产生第二相的反相电压，并且电容器Cout 1 被放电以产生反相电压，并且第二电容器被充电以在第三相中产生升压电压。 因此，升压反相转换器具有较低的峰值电感电流和较小的功率损耗，并且对升压反相转换器的开关设计的限制放宽。

公开(公告)号：US20060109046A1

公开(公告)日：2006-05-25

申请号：US11108742

申请日：2005-04-19

申请人： Chun-Yen Huang ,  Hung-Der Su ,  Jing-Meng Liu ,  Chung-Lung Pai ,  Shih-Hui Chen ,  Yang-Ping Hung

发明人： Chun-Yen Huang ,  Hung-Der Su ,  Jing-Meng Liu ,  Chung-Lung Pai ,  Shih-Hui Chen ,  Yang-Ping Hung

IPC分类号： H03K17/00

CPC分类号： H03K17/0822 ,  H03K3/00 ,  H03K17/00 ,  H03K17/18 ,  H03K17/6871

摘要： A method, which is for determining switching state of a transistor-based switching device that includes a set of transistors, includes the steps of: applying a bias voltage to a transistor having a fastest response so as to dispose the transistors in the set in a desired transistor state; detecting a voltage level at a transistor having a slowest response to the bias voltage; and comparing the detected voltage level with a predetermined threshold voltage level in order to determine the switching state of the switching device. A transistor-based switching device is also disclosed.

摘要翻译： 一种用于确定包括一组晶体管的基于晶体管的开关器件的开关状态的方法包括以下步骤：将偏置电压施加到具有最快响应的晶体管，以将晶体管置于该组中的晶体管中 所需晶体管状态; 检测对所述偏置电压具有最慢响应的晶体管的电压电平; 以及将检测到的电压电平与预定阈值电压电平进行比较，以便确定开关器件的开关状态。 还公开了一种基于晶体管的开关器件。

公开(公告)号：US20050275711A1

公开(公告)日：2005-12-15

申请号：US11149292

申请日：2005-06-10

申请人： Jing-Meng Liu ,  Chung-Lung Pai ,  Hung-Der Su

发明人： Jing-Meng Liu ,  Chung-Lung Pai ,  Hung-Der Su

IPC分类号： B41J2/47 ,  H05B33/08

CPC分类号： H05B33/0857 ,  H05B33/0818 ,  H05B33/0827 ,  Y02B20/347

摘要： In a LED driver using a depletion mode transistor to serve as a current source, the depletion mode transistor is self-biased for providing a driving current to drive at least one LED, thereby requesting no additional control circuit to control the depletion mode transistor. The driving current is independent on the supply voltage coupled to the at least one LED, thereby requesting no additional voltage regulator, reducing the circuit size, and lowering the cost.

摘要翻译： 在使用耗尽型晶体管作为电流源的LED驱动器中，耗尽型晶体管是自偏置的，用于提供驱动电流以驱动至少一个LED，从而不需要额外的控制电路来控制耗尽型晶体管。 驱动电流独立于耦合到至少一个LED的电源电压，从而不需要额外的电压调节器，减小电路尺寸并降低成本。

公开(公告)号：US06747857B1

公开(公告)日：2004-06-08

申请号：US10062706

申请日：2002-02-01

申请人： Jian-Hsing Lee ,  Hung-Der Su ,  Jiaw-Ren Shih

发明人： Jian-Hsing Lee ,  Hung-Der Su ,  Jiaw-Ren Shih

IPC分类号： H02H900

CPC分类号： H03K17/0822 ,  H01L27/0266 ,  H03K17/6872

摘要： A novel device and process is described for an ESD protection device for complimentary cascaded NMOS output circuit strings. The invention consists of a clamping NMOS with gate connected to the input or output pad through a diode and connected to ground through a resistor. The clamping device drain is connected to the signal gate of the active output NMOS and the clamping device source is connected to ground. An ESD event causes the diode to go into breakdown mode and the conduction current across the resistor places a positive voltage on the clamping device gate turning the clamping device on. This clamps the active NMOS signal gate to ground assuring that the output NMOS remains in an off condition during the ESD event. This prevents any damage due to high current flow through the active, or used output inverter string.

摘要翻译： 对于用于互补级联的NMOS输出电路串的ESD保护器件描述了一种新颖的器件和工艺。 本发明包括一个钳位NMOS，其栅极通过二极管连接到输入或输出焊盘，并通过电阻器连接到地。 钳位装置漏极连接到有源输出NMOS的信号栅极，钳位装置源连接到地。 ESD事件导致二极管进入击穿模式，并且电阻两端的导通电流在夹紧装置门上施加正电压，使夹紧装置打开。 这将有源NMOS信号栅极钳位到地，确保在ESD事件期间输出NMOS保持关断状态。 这可以防止由于高电流流过有源或使用的输出逆变器串造成的任何损坏。

公开(公告)号：US06653709B2

公开(公告)日：2003-11-25

申请号：US10213612

申请日：2002-08-07

申请人： Yi-Hsu Wu ,  Hung-Der Su ,  Jian-Hsing Lee ,  Boon-Khim Liew

发明人： Yi-Hsu Wu ,  Hung-Der Su ,  Jian-Hsing Lee ,  Boon-Khim Liew

IPC分类号： H01L2972

CPC分类号： H01L27/092 ,  H01L21/823814 ,  H01L27/0266

摘要： A new cascaded NMOS transistor output circuit with enhanced ESD protection is achieved. A driver PMOS transistor has the source connected to a voltage supply, the gate connected to the input signal, and the drain connected to the output pad. A dummy PMOS transistor has the source and the gate connected to the voltage supply, and the drain connected to the output pad. A driver NMOS cascaded stack comprises first and second NMOS transistors. The first NMOS transistor has the source connected to ground and the gate connected to the input signal. The second NMOS transistor has the gate connected to the voltage supply, the source connected to the first NMOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source. A dummy NMOS cascaded stack comprises third and fourth NMOS transistors. The third NMOS transistor has the gate and the source connected to ground. The fourth NMOS transistor has the gate connected to the voltage supply, the source connected to the third MOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source.

公开(公告)号：US06348382B1

公开(公告)日：2002-02-19

申请号：US09392391

申请日：1999-09-09

申请人： Hung-Der Su ,  Chrong Jung Lin ,  Jong Chen ,  Wen-Ting Chu

发明人： Hung-Der Su ,  Chrong Jung Lin ,  Jong Chen ,  Wen-Ting Chu

IPC分类号： H01L218234

CPC分类号： H01L21/823857 ,  H01L21/823814

摘要： A new process is provided whereby LDD regions for HV CMOS devices and for LV CMOS devices are created using one processing sequence. The gate electrodes for both the High Voltage and the Low Voltage devices are created on the surface of a silicon substrate. The High Voltage LDD (HVLDD) is performed self-aligned with the HV CMOS gate electrode, a gate anneal is performed for both the HV and the LV CMOS devices. The Low Voltage LDD (LVLDD) is performed self-aligned with the LV CMOS gate electrodes. The gate electrodes of the CMOS devices are after this completed with the formation of the gate spacers, the source/drain implants and the back-end processing that is required for CMOS devices.

摘要翻译： 提供了一种新的方法，由此使用一个处理顺序创建用于HV CMOS器件和LV CMOS器件的LDD区域。 用于高电压和低电压器件的栅电极都在硅衬底的表面上产生。 高压LDD（HVLDD）与HV CMOS栅电极自对准，对HV和LV CMOS器件进行栅极退火。 低压LDD（LVLDD）与LV CMOS栅电极自对准。 在CMOS器件的栅电极完成之后，形成栅极间隔物，源极/漏极注入和CMOS器件所需的后端处理。

公开(公告)号：US06297098B1

公开(公告)日：2001-10-02

申请号：US09431236

申请日：1999-11-01

申请人： Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen ,  Wen-Ting Chu

发明人： Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen ,  Wen-Ting Chu

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L21/26586

摘要： A method is disclosed for forming LDDs (Lightly Doped Drains) in high voltage devices employed in non-volatile memories and DDDs (Doubly Doped Drains) in flash memory applications. The high voltage device is formed by using two successive ion implantations at a tilted angle which provides an improved gradation of doped profile near the junction and the attendant improvement in junction breakdown at higher voltages. The doubly doped drain in a stacked flash memory cell is also formed by two implantations, but at an optimum tilt-angle, where the first implantation is lightly doped, and the second, heavily doped. The resulting DDD provides faster program speed, reduced program current, increase read current and reduced drain disturb in the flash memory cell.

摘要翻译： 公开了一种用于在闪速存储器应用中用于非易失性存储器和DDD（双掺杂漏极）的高压器件中形成LDD（轻掺杂漏极）的方法。 高压器件通过以倾斜角度使用两个连续的离子注入形成，其提供了接合点附近的掺杂分布的改进的灰度级，并且在更高的电压下提高了结点击穿。 层叠闪存单元中的双掺杂漏极也通过两次注入形成，但是以最佳倾角形成，其中第一次注入被轻掺杂，而第二次重掺杂。 由此产生的DDD提供更快的编程速度，减少编程电流，增加读取电流和减少闪存单元中的漏极干扰。

公开(公告)号：US6153494A

公开(公告)日：2000-11-28

申请号：US310257

申请日：1999-05-12

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su

IPC分类号： H01L21/762 ,  H01L21/8247 ,  H01L27/115 ,  H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/76224 ,  H01L27/115

摘要： A method is provided for forming a stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling. This is accomplished by first depositing an unconventionally high or thick layer of nitride and then forming a shallow trench isolation (STI) through the nitride layer into the substrate, filling the STI with isolation oxide, removing the nitride thus leaving behind a deep opening about the filled STI, filling conformally the opening with a first polysilicon layer to form a floating gate, forming interpoly oxide layer over the floating gate, and then forming a second polysilicon layer to form the control gate and finally forming the self-aligned source of the stacked-gate flash memory cell of the invention. A stacked-gate flash memory cell is also provided having a shallow trench isolation with a high-step of oxide and high lateral coupling.

摘要翻译： 提供一种用于形成具有高阶氧化物和高横向耦合的浅沟槽隔离的堆叠栅极快闪存储器单元的方法。 这是通过首先沉积非常规高或较厚的氮化物层，然后通过氮化物层形成浅沟槽隔离（STI）到衬底中，用隔离氧化物填充STI，从而除去氮化物，从而留下围绕 填充STI，用第一多晶硅层保形地填充开口以形成浮置栅极，在浮置栅极上形成多晶硅层，然后形成第二多晶硅层以形成控制栅极，并最终形成堆叠的自对准源 本发明的闪存单元。 还提供了堆叠栅极闪存单元，其具有具有高阶氧化物和高横向耦合的浅沟槽隔离。