公开(公告)号：US20170278752A1

公开(公告)日：2017-09-28

申请号：US15459991

申请日：2017-03-15

Applicant: IMEC VZW

Inventor： Julien Ryckaert ,  Juergen Boemmels

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/528 ,  H01L21/311 ,  H01L23/522 ,  H01L27/088 ,  H01L21/3213 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0886 ,  H01L29/66545

Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to electrical contacts to a transistor device, and a method of making such electrical contacts. In one aspect, a method of forming one or more self-aligned gate contacts in a semiconductor device includes providing a substrate having formed thereon at least one gate stack, where the gate stack includes a gate dielectric and a gate electrode formed over an active region in or on the substrate, and where the substrate further has formed thereon a spacer material coating lateral sides of the at least one gate stack. The method additionally includes selectively recessing the gate electrode of the at least one gate stack against the spacer material, thereby creating a first set of recess cavities. The method additionally includes filling the first set of recess cavities with a dielectric material gate cap. The method additionally includes etching at least one via above the at least one gate stack and through the dielectric material gate cap, where etching the at least one via comprises selectively etching against the spacer material, thereby exposing the gate electrode. The method further includes forming, in the at least one via, a gate contact electrically connecting the gate electrode.

公开(公告)号：US20240266349A1

公开(公告)日：2024-08-08

申请号：US18433779

申请日：2024-02-06

Applicant: IMEC VZW

Inventor： Gioele Mirabelli ,  Juergen Boemmels ,  Julien Ryckaert

IPC: H01L27/092 ,  H01L23/528 ,  H01L27/06 ,  H10B10/00

CPC classification number: H01L27/092 ,  H01L23/5286 ,  H01L27/0688 ,  H10B10/12

Abstract: This disclosure relates to complementary field effect transistor (CFET) devices, and provides improved routability of the transistor structures in a CFET cell. The disclosure presents a CFET cell that includes a first transistor structure in a first tier and a second transistor structure in a second tier above the first tier. A first power rail is arranged below the first tier and connected to the first transistor structure from below, and a second power rail is formed in a first metal layer and connected to the second transistor structure from a first side. A set of signal routing lines formed in a second metal layer above the second tier is connected to the first and second transistor structure from above. Further, a signal routing structure formed in a metal zero (M0) layer is connected to the first transistor structure and/or to the second transistor structure from a second side.

公开(公告)号：US11381242B2

公开(公告)日：2022-07-05

申请号：US17063003

申请日：2020-10-05

Applicant: IMEC VZW

Inventor： Francky Catthoor ,  Edouard Giacomin ,  Juergen Boemmels ,  Julien Ryckaert

IPC: H03K19/17736 ,  H01L27/06

Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell.

公开(公告)号：US20210183711A1

公开(公告)日：2021-06-17

申请号：US17110604

申请日：2020-12-03

Applicant: IMEC vzw

Inventor： Eugenio Dentoni Litta ,  Juergen Boemmels ,  Julien Ryckaert ,  Naoto Horiguchi ,  Pieter Weckx

IPC: H01L21/8238 ,  H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

Abstract: In one aspect, a method of forming a semiconductor device, can comprise forming a first transistor structure and a second transistor structure separated by a trench. The first and the second transistor structures can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. A first and a second spacer can beformed in the trench at sidewalls of the transistor structures, both protruding above a top surface of the transistor structures. The method can comprise applying a first mask layer including an opening exposing the first spacer at a first source/drain portion of the first transistor structure and covering the second spacer, partially etching the exposed first spacer through the opening, exposing at least parts of a sidewall of the first source/drain portion of the first transistor structure, and removing the mask layer. The method can further comprise depositing a contact material over the transistor structures and the first and second spacer, filling the trench and contacting the first source/drain portion of the first transistor structure, and etching back the contact material layer below a top surface of the second spacer.

公开(公告)号：US20210020516A1

公开(公告)日：2021-01-21

申请号：US16931230

申请日：2020-07-16

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Yong Kong Siew ,  Juergen Boemmels

IPC: H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/027

Abstract: In one aspect, a method can include forming, by self-aligned multiple patterning, a first pattern of regularly spaced mandrels on a layer to be patterned; forming hard mask spacers on sidewalls of the mandrels, thereby forming a second pattern formed of assemblies comprising a mandrel and hard mask spacers on sidewalls thereof; and etching the second pattern in the layer to be patterned.

公开(公告)号：US10546930B2

公开(公告)日：2020-01-28

申请号：US15980603

申请日：2018-05-15

Applicant: IMEC VZW

Inventor： Juergen Boemmels

IPC: H01L29/78 ,  H01L29/15 ,  H01L29/66

Abstract: The disclosed technology generally relates to semiconductor fabrication and more particularly to a method of forming vertical channel devices. In one aspect, a method of forming vertical channel devices includes providing a semiconductor structure that includes a substrate and a plurality of vertical channel structures. The method additionally includes surrounding the vertical channel structures with respective wrap-around gates. The method additionally includes forming enlarged top portions by selectively growing a doped semiconductor material on respective top portions of at least a subset of the vertical channel structures. The method further includes forming a top electrode on each of the enlarged top portions.

公开(公告)号：US10374084B2

公开(公告)日：2019-08-06

申请号：US15980611

申请日：2018-05-15

Applicant: IMEC vzw

Inventor： Juergen Boemmels

IPC: H01L21/8238 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/15 ,  H01L29/66

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to vertical channel devices and a method of making the same. In one aspect, a method of forming vertical channel devices includes forming a first vertical channel structure extending from a first bottom electrode region and a second vertical channel structure extending from a second bottom electrode region. The first and the second vertical channel structures protrude from a dielectric layer covering the first and second bottom electrode regions. The method additionally comprises forming a first hole exposing the first bottom electrode region and a second hole exposing the second bottom electrode region, where the first and the second holes extending vertically through the dielectric layer. The method additionally includes forming a conductive pattern including a set of discrete pattern parts on the dielectric layer. Forming the conductive pattern includes forming a first pattern part including a first gate portion wrapping around a protruding portion of the first vertical channel structure, where a first bottom electrode contact portion is arranged in the second hole, and a first cross-coupling portion extending between the first bottom electrode contact portion and the first gate portion. Forming the conductive pattern additionally includes forming a second pattern part including a second gate portion wrapping around a protruding portion of the second vertical channel structure, where a second bottom electrode contact portion is arranged in the first hole, and a cross-coupling portion extending between the second bottom electrode contact portion and the second gate portion.

公开(公告)号：US10242907B2

公开(公告)日：2019-03-26

申请号：US15615299

申请日：2017-06-06

Applicant: IMEC VZW

Inventor： Julien Ryckaert ,  Juergen Boemmels ,  Christopher Wilson

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/528

Abstract: A method for forming a pattern for an integrated circuit is disclosed. In one aspect, the method includes (a) providing a hardmask layer; (b) overlaying the hard mask layer with a set of parallel material lines delimiting gaps therebetween; and (c) providing a spacer layer following the shape of the material layer. The method further includes (d) removing a top portion of the spacer layer, thereby forming spacer lines alternatively separated by material lines and by gaps; and (e) providing a blocking element in a portion of a gap. The method also includes (f) etching selectively the hard mask layer by using the material layer, the spacer lines and the blocking element as a mask, thereby providing a first set of parallel trenches in the hardmask layer, wherein a trench has a blocked portion; and (g) selectively removing the blocking element.

公开(公告)号：US20180342584A1

公开(公告)日：2018-11-29

申请号：US15980603

申请日：2018-05-15

Applicant: IMEC VZW

Inventor： Juergen Boemmels

IPC: H01L29/15 ,  H01L29/66 ,  H01L29/78

Abstract: The disclosed technology generally relates to semiconductor fabrication and more particularly to a method of forming vertical channel devices. In one aspect, a method of forming vertical channel devices includes providing a semiconductor structure that includes a substrate and a plurality of vertical channel structures. The method additionally includes surrounding the vertical channel structures with respective wrap-around gates. The method additionally includes forming enlarged top portions by selectively growing a doped semiconductor material on respective top portions of at least a subset of the vertical channel structures. The method further includes forming a top electrode on each of the enlarged top portions.

公开(公告)号：US20170256451A1

公开(公告)日：2017-09-07

申请号：US15451175

申请日：2017-03-06

Applicant: IMEC vzw

Inventor： Juergen Boemmels ,  Zsolt Tokei ,  Christopher Wilson

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295

Abstract: An interconnect structure and a method for forming it is disclosed. In one aspect, the method includes the steps of providing a first entity. The first entity includes a first set of line structures. The first set of line structures include a first set of conductive lines, and a first set of dielectric lines made of a first dielectric material and aligned with and overlaying the first set of conductive lines. The first entity also includes gaps separating the line structures and filled with a second dielectric material of such a nature that the first dielectric material can be selectively etched with respect to the second dielectric material. The method also includes providing a patterned mask on the first entity. The method further includes etching selectively the first dielectric material through the patterned mask so as to form one or more vias in the first dielectric material. The method also includes removing the patterned mask.